Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS

• US 8,497,865 B2
• Filed: 12/31/2006
• Issued: 07/30/2013
• Est. Priority Date: 12/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Leviathan, Yaniv, Bakalash, Reuven
• Primary Examiner(s): WANG, JIN CHENG
• Application Number:
  US11/648,160
• Publication Number:
  US 20080158236A1
• Time in Patent Office: 2,403 Days
• Field of Search: 345501-505, 345519-522
• US Class Current: 345/501
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Claims

1. A method of recompositing partial pixel data within a graphics processing unit (GPU) of a multi-GPU graphics processing subsystem so as to produce images for display on a screen,

wherein said partial pixel data is generated by a plurality of GPUs operating according to an object division mode of graphics parallelization, wherein said object division mode includes a rendering phase of operation and a recomposition phase of operation, wherein each GPU has one or more programmable shaders, and a frame buffer (FB) having depth buffers for buffering pixel depth values and color frame buffers for buffering pixel color values, and wherein at least one of said GPUs is a display-designated GPU that is connectable to said screen for displaying images produced by said multi-GPU graphics processing subsystem, and at least one of said GPUs is a non-display-designated GPU, said method comprising the sequence of steps of:

(a) entering said rendering phase, and programming and configuring said one or more programmable shaders within said display designated GPU and said one or more non-display-designated GPUs, to perform rendering operations that produce partial results;

(b) passing geometric data and commands to said plurality of GPUs according to said object division mode of parallelization;

(c) using said one or more programmable shaders within said display designated GPO and said one or more non-display-designated GPUs, to generate partial results for said depth and color frame buffers according to said object division mode; and

(d) exiting said rendering phase, and entering said recomposition phase, and reprogramming and reconfiguring said one or more programmable shaders within said display designated GPU, to perform recomposition operations that produce an image for display;

(e) moving said partial results to said display-designated GPU;

(f) using said one or more programmable shaders within said display-designated GPU to produce an image for display; and

(g) displaying said image on said screen.

2. The method of claim 1, said one or more programmable shaders comprises programmable fragment shaders.

3. The method of claim 1, said one or more programmable shaders comprises programmable vertex shaders.

4. The method of claim 2, further comprising the recomposition steps of said programmable shaders in the said display-designated GPU,

(i) comparing, on a pixel-by-pixel basis, the pixel depth (z) values of opaque rendered objects buffered in said depth buffers, and representative of partial results, and

(ii) at each x,y location in said color frame buffer of said display-designated GPU, selecting the pixel having the lowest depth value representative of the pixel closet to the viewer along a viewing direction, and

(iii) moving the associated color value of the selected pixel to the corresponding x.y location in said color frame buffer of said display-designated GPU, for composition with other selected pixels, so as to produce an image for subsequent display.

5. A multi-GPU graphics processing subsystem for use in a computing system, said graphics processing subsystem comprising:

a plurality of GPUs operating according to object division mode of graphics parallelization,

wherein said object division mode includes a rendering phase of operation and a recomposition phase of operation;

wherein at least one of said GPUs is a display-designated GPU that is connectable to a screen for displaying images produced by said multi-GPU graphics processing subsystem, and at least one of said GPUs is a non-display-designated GPU;

wherein each said GPU includes (i) one or more programmable shaders, and (ii) video memory including a frame buffer (FB) having depth buffers for buffering pixel depth values and color frame buffers for buffering pixel color values; and

wherein for images to be generated and displayed on said screen, geometric data and graphics commands are distributed to said plurality of GPUs according to said object division mode of parallelization, wherein the multi-GPU graphics processing subsystem supports the following data processing steps;

(a) upon entering said rendering phase, programming and configuring said one or more programmable shaders within said display designated GPU and said one or more non-display-designated GPUs, to perform rendering operations that produce partial results;

(b) passing geometric data and commands to said plurality of GPUs according to said object division mode of parallelization;

(c) using said one or more programmable shaders within said display designated GPU and said one or more non-display-designated GPUs, to generate partial results for depth and color frame buffers according to the object division mode of parallelization;

(d) exiting said rendering phase, and entering said recomposition phase, and reprogramming and reconfiguring said one or more programmable shaders within said display designated GPU, to perform recomposition operations that produce an image for display; and

(e) displaying said image on said screen.

6. The subsystem of claim 5, wherein said one or more programmable shaders comprise programmable fragment shaders.

7. The subsystem of claim 5, wherein said one or more programmable shaders comprise programmable vertex shaders.

8. The subsystem of claim 5, wherein said programmable shaders in said display-designated GPU, perform the following operations within said display-designated GPU:

(i) comparing, on a pixel-by-pixel basis, the pixel depth (z) values of opaque rendered objects,

(ii) at each x,y location, selecting the pixel having the lowest depth value representative of the pixel closet to the viewer along said viewing direction,

(iii) moving the associated color value of the selected pixel to the corresponding x,y location in said color frame buffer, for composition with other selected pixels to produce an image for subsequent display; and

(iv) displaying said image pixel data on said screen.