Interconnect structure

• US 8,498,131 B2
• Filed: 08/09/2011
• Issued: 07/30/2013
• Est. Priority Date: 07/26/2007
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Fillion, Raymond Albert, Durocher, Kevin Matthew, Saia, Richard Joseph, Woychik, Charles Gerard
• Primary Examiner(s): Thompson, Timothy
• Assistant Examiner(s): Aychillhum, Andargie M
• Application Number:
  US13/136,736
• Publication Number:
  US 20110299821A1
• Time in Patent Office: 721 Days
• Field of Search: 361/783, 361/760, 361/729, 361/748, 257/680
• US Class Current: 361/783
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.

Claims

1. An article comprising:

a frame assembly comprising;

a frame base having a first surface and a second surface, and the frame base being conductive;

a first frame insulative layer disposed on the frame base first surface;

a frame aperture extending through the frame base;

a frame conductive layer disposed on the first frame insulative layer; and

a frame connector supported by the frame base in communication with at least a portion of the frame conductive layer;

an insulative web having a first surface and a second surface;

an insulative web conductive layer supported by the insulative web;

a logic device supported by the insulative web and disposed within the frame aperture;

a device connector communicating with the insulative web conductive layer, the frame connector communicating with the frame conductive layer and the insulative web conductive layer.

2. The article as defined in claim 1, wherein the logic device is an optical device, and wherein the frame connector and device connector are optically transmissive, and the frame conductive layer and the insulative web conductive layer comprise waveguides.

3. An electronic component, comprising:

a frame supporting a web and a logic device secured to the web, and optical or electronic circuitry supported by the frame, and the supported optical or electronic circuitry communicates with the logic device, wherein the frame has an outer surface that defines a peripheral edge and the optical or electronic circuitry comprises an I/O port that is disposed on the peripheral edge to allow the logic device to communicate therethrough, wherein the frame has an inner surface defining an aperture, and the web is supported within the aperture, wherein the frame supplies structural rigidity to the component.

4. The component as defined in claim 3, wherein the electronic circuitry comprises one or more passive components.

5. The component as defined in claim 3, further comprising an electrical device connector through which the logic device communicates with the electronic circuitry.

6. The component as defined in claim 3, further comprising an optical device connector through which the logic device communicates with the optical circuitry.

7. The component as defined in claim 6, wherein the optical connector is an optical fiber or an optical waveguide.

8. The component as defined in claim 3, wherein the frame defines an aperture through a body of the frame through which a device connector extends.

9. The component as defined in claim 3, wherein the frame defines an open-sided channel through a body of the frame through which a device connector extends.

10. The component as defined in claim 3, wherein the frame is electrically conductive, and further comprising a dielectric layer disposed on a surface of the frame and adjacent to the electronic circuitry.