Data storage in analog memory cells using modified pass voltages
First Claim
1. A method for data storage, comprising:
- storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell;
verifying the storage value written into the target memory cell while biasing the other memory cells in the group with respective first pass voltages;
after writing and verifying the storage value, reading the storage value from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells; and
reconstructing the data responsively to the read storage value.
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Abstract
A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell. The storage value written into the target memory cell is verified while biasing the other memory cells in the group with respective first pass voltages. After writing and verifying the storage value, the storage value is read from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells. The data is reconstructed responsively to the read storage value.
566 Citations
40 Claims
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1. A method for data storage, comprising:
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storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell; verifying the storage value written into the target memory cell while biasing the other memory cells in the group with respective first pass voltages; after writing and verifying the storage value, reading the storage value from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells; and reconstructing the data responsively to the read storage value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method, comprising:
reading an output storage value from a target memory cell in a group of memory cells that are connected in series, wherein the reading includes biasing one of the other memory cells in the group with a pass voltage that is based on a storage value of the other memory cell. - View Dependent Claims (16, 17)
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18. A method, comprising:
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reading an output storage value from a target memory cell in a group of memory cells that are connected in series; wherein the reading includes; applying a read threshold to the target memory cell; and biasing one of the other memory cells in the group with a pass voltage that is based on the read threshold. - View Dependent Claims (19, 20)
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21. An apparatus, comprising:
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an interface, configured to communicate with a memory comprising a group of memory cells that are connected in series; and circuitry, configured to; store data in a target analog memory cell in the group by writing a storage value into the target memory cell; verify the storage value written into the target memory cell while biasing the other memory cells in the group with respective first pass voltages; and read the storage value from the target memory cell, after writing and verifying the storage value, wherein, to read the storage value, the circuitry is configured to bias the other memory cells in the group with respective second pass voltages; wherein one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cell. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. An apparatus, comprising:
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an interface configured to communicate with a memory comprising a group of multi-level memory cells connected in series; and circuitry, which is configured to; read an output storage value from a target memory cell in the group, wherein, to read the output storage value, the circuitry is configured to bias one of the other memory cells in the group with a pass voltage that is based on a value stored in one of the other memory cells. - View Dependent Claims (36, 37)
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38. An apparatus, comprising:
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an interface, configured to communicate with a memory comprising a group of memory cells that are connected in series; and circuitry, configured to; read an output storage value from a target memory cell in the group using a read voltage; wherein, to read the output storage value, the circuitry is configured to bias one of the other memory cells in the group with a pass voltage that depends on the read voltage. - View Dependent Claims (39, 40)
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Specification