Systems and methods for improving error distributions in multi-level cell memory systems

• US 8,498,154 B1
• Filed: 05/14/2012
• Issued: 07/30/2013
• Est. Priority Date: 03/10/2008
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Yang, Xueshi
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/470,884
• Time in Patent Office: 442 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.04, 365/185.09, 365/185.12, 365/185.17, 365/185.23, 365/189.011, 365/189.14, 365/230.04, 365/230.06
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 8/10 Decoders

Claims