Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a substrate;
device regions formed in the substrate to extend in a first direction which is parallel to a surface of the substrate;
a memory cell array region including a plurality of memory cells disposed on the device regions;
bit lines disposed above the substrate to extend in the first direction;
a sense amplifier circuit electrically connected to the bit lines at ends of the bit lines on one side; and
bit line contacts disposed on the device regions to electrically connect the device regions to the bit lines,whereinthe memory cell array region includes first to N-th regions where N is an integer of two or more,a K-th region is located at a greater distance from the sense amplifier circuit than a (K−
1)-th region, where K is an arbitrary integer of 2 to N,contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−
1)-th region, anda width of each device region is constant in the memory cell array region.
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Abstract
A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines, and bit line contacts connecting device regions to bit lines. The memory cell array region includes first to N-th regions where N is an integer of two or more, and a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N. Contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, each device region having constant width in the memory cell array region.
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Citations
19 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a substrate; device regions formed in the substrate to extend in a first direction which is parallel to a surface of the substrate; a memory cell array region including a plurality of memory cells disposed on the device regions; bit lines disposed above the substrate to extend in the first direction; a sense amplifier circuit electrically connected to the bit lines at ends of the bit lines on one side; and bit line contacts disposed on the device regions to electrically connect the device regions to the bit lines, wherein the memory cell array region includes first to N-th regions where N is an integer of two or more, a K-th region is located at a greater distance from the sense amplifier circuit than a (K−
1)-th region, where K is an arbitrary integer of 2 to N,contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−
1)-th region, anda width of each device region is constant in the memory cell array region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A nonvolatile semiconductor memory device comprising:
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a substrate; device regions formed in the substrate to extend in a first direction which is parallel to a surface of the substrate; a memory cell array region including a plurality of memory cells disposed on the device regions; first bit lines disposed above the substrate to extend in the first direction, and electrically connected to a first sense amplifier circuit on the substrate at ends of the first bit lines on one side; second bit lines disposed above the substrate to extend in the first direction, and electrically connected to a second sense amplifier circuit on the substrate at ends of the second bit lines on the other side; first bit line contacts disposed on the device regions to electrically connect the device regions to the first bit lines; and second bit line contacts disposed on the device regions to electrically connect the device regions to the second bit lines, wherein the memory cell array region includes first to N-th regions where N is an integer of two or more, a K-th region is located at a greater distance from the first sense amplifier circuit than a (K−
1)-th region, where K is an arbitrary integer of 2 to N,contact resistance of the first bit line contacts in the K-th region is lower than contact resistance of the first bit line contacts in the (K−
1)-th region,the K-th region is located at a smaller distance from the second sense amplifier circuit than the (K−
1)-th region,contact resistance of the second bit line contacts in the K-th region is higher than contact resistance of the second bit line contacts in the (K−
1)-th region, anda width of each device region is constant in the memory cell array region. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification