Method and apparatus to authenticate a power supply

• US 8,499,179 B2
• Filed: 06/06/2012
• Issued: 07/30/2013
• Est. Priority Date: 12/19/2005
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Bailey, Douglas John, Balakrishnan, Balu
• Primary Examiner(s): LOUIE, OSCAR A
• Application Number:
  US13/490,371
• Publication Number:
  US 20120246495A1
• Time in Patent Office: 419 Days
• Field of Search: 713/300
• US Class Current: 713/300
• CPC Class Codes: H02J 1/00 Circuit arrangements for dc mains or dc distribution networks
• CPC Class Codes: H02J 13/00002 characterised by monitoring
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 10/30 State monitoring, e.g. fault, temperature monitoring, insulator monitoring, corona discharge

Abstract

A power bus monitor for use in an electronic product is coupled to receive power from an external power supply. The power bus monitor includes a signal detector coupled to an output of the external power supply to receive and demodulate information encoded on the output of the external power supply into a sequence of bits. A decoder is coupled to receive the sequence of bits from the signal detector and decrypt the sequence of bits. A logical comparator is coupled to receive the sequence of bits decrypted by the decoder. The logical comparator is coupled to assert an authentication signal indicating the external power supply is authorized to provide power to the electronic product when the logical comparator recognizes the sequence of bits decrypted by the decoder as a key.

Claims

1. A power bus monitor for use in an electronic product coupled to receive power from an external power supply, comprising:

a signal detector circuit coupled to an output of the external power supply to receive and demodulate information encoded on the output of the external power supply into a sequence of bits;

a decoder circuit coupled to receive the sequence of bits from the signal detector circuit and decrypt the sequence of bits; and

a logical comparator circuit coupled to receive the sequence of bits decrypted by the decoder circuit, the logical comparator circuit coupled to assert an authentication signal indicating the external power supply is authorized to provide power to the electronic product when the logical comparator circuit recognizes the sequence of bits decrypted by the decoder circuit as a key, wherein the decoder circuit includes a linear feedback shift register that uses an encrypting polynomial and the key to decrypt the sequence of bits.

2. The power bus monitor of claim 1 wherein the output of the external power supply includes no more than two conductors over which the power from the external power supply are transferred to the electronic product and over which the information encoded on the output of the external power supply is transferred to the signal detector circuit.

3. The power bus monitor of claim 1 wherein the information is encoded on the output of the external power supply by modulating a phase of ripple at the output of the external power supply during start-up.

4. The power bus monitor of claim 1 wherein the information is encoded on the output of the external power supply by modulating an output quantity at the output of the external power supply during start-up.

5. The power bus monitor of claim 4 wherein the output quantity at the output of the external power supply during start-up comprises an output voltage.

6. The power bus monitor of claim 4 wherein the output quantity at the output of the external power supply during start-up comprises an output current.

7. The power bus monitor of claim 4 wherein the information is encoded during start-up at times when an amplitude of the output quantity at the output of the external power supply crosses a threshold.

8. The power bus monitor of claim 4 wherein the authentication signal is generated in response to a comparison of a duration of time that the output quantity is above an upper threshold compared to a duration of time that the output quantity is below a lower threshold.