Semiconductor device and data processing system
First Claim
1. A semiconductor device comprising:
- a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions;
a plurality of controlled circuits subject to control of the stop and supply of the power and clocks;
power and clock control circuits which control the stop and supply of the power and clocks relative to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and
a forcible release control circuit which forcibly releases the supply and stop of the power and clocks that are conducted on one or more predetermined controlled circuits by the power and clock control circuits, only during a period required by a power and clock request signal outputted from a requesting circuit, to thereby temporarily resume supply of the power and clocks to the one or more predetermined controlled circuits and thus enable operation of at least one resource required by the requesting circuit.
2 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor device has reduced power consumption and processing time associated with the release of a low power consumption state set by a central processing unit thereof. The semiconductor device controls a relationship between a forcible release and reset of the low power consumption state previously set by the central processing unit. In one embodiment, a forcible release control circuit forcibly releases the supply and stop of power and clocks previously set to one or more controlled circuits, only during a period required by a signal outputted from a requesting circuit, which requesting circuit may be either internal to the device or external to the device. Once the request signal from the requesting circuit has ended, the controlled circuits and, if appropriate, the central processing unit as well, are restored to the original low power consumption state.
16 Citations
40 Claims
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1. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which control the stop and supply of the power and clocks relative to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks that are conducted on one or more predetermined controlled circuits by the power and clock control circuits, only during a period required by a power and clock request signal outputted from a requesting circuit, to thereby temporarily resume supply of the power and clocks to the one or more predetermined controlled circuits and thus enable operation of at least one resource required by the requesting circuit.
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2. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which control the stop and supply of the power and clocks relative to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks that are conducted on one or more predetermined controlled circuits by the power and clock control circuits, only during a period required by a power and clock request signal outputted from a requesting circuit; wherein the power and clock control circuits comprise; control registers which hold control data for controlling the stop and supply of the power and clocks to the plurality of the controlled circuits, and control logics which input the control data in the control registers and an instruction signal to the forcible release control circuit to thereby control the supply and stop of the power and clocks relative to the controlled circuits, and wherein each of the control logics; allows the power and clocks to be supplied when the control data indicates the supply of the power and clocks, allows the power and clocks to stop when the control data indicates the stop of the power and clocks and the power and clock request signal indicates no request for the supply of the power and clocks, and allows the power and clocks to be supplied when the control data indicates the stop of the power and clocks and the power and clock request signal requests the supply of the power and clocks.
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3. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which control the stop and supply of the power and clocks relative to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks that are conducted on one or more predetermined controlled circuits by the power and clock control circuits, only during a period required by a power and clock request signal outputted from a requesting circuit; wherein the forcible release control circuit receives state signals each indicative of a state of the supply and stop of power and clocks to the controlled circuits from the power and clock control circuits and controls a first timing provided to release the supply and stop of the power and clocks and a second timing provided to restore the same from the release, referring to the received state signals. - View Dependent Claims (4, 5)
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6. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which control the stop and supply of the power and clocks relative to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; a forcible release control circuit which forcibly releases the supply and stop of the power and clocks that are conducted on one or more predetermined controlled circuits by the power and clock control circuits, only during a period required by a power and clock request signal outputted from a requesting circuit; and an interrupt controller which causes the power and clock control circuits to resume the supply of power and clocks to the central processing unit whose supply has been stopped, in response to an interrupt request supplied from the requesting circuit; wherein the requesting circuit comprises a data processing circuit for processing data fetched therein, and wherein said one or more predetermined controlled circuits comprises a first interface circuit for supplying data to be fetched into the requesting circuit, based on a request issued from the requesting circuit. - View Dependent Claims (7, 8, 9)
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10. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which respectively control the stop and supply of the power and clocks to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks, conducted on one or more predetermined controlled circuits by the power and clock control circuits only during a period required by a power and clock request signal received at a first external input terminal of the semiconductor device, to thereby temporarily resume supply of the power and clocks to the one or more predetermined controlled circuits and thus enable operation of at least one resource required by an external circuit issuing said request signal. - View Dependent Claims (11)
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12. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which respectively control the stop and supply of the power and clocks to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks, conducted on one or more predetermined controlled circuits by the power and clock control circuits only during a period required by a power and clock request signal received at a first external input terminal of the semiconductor device; wherein the power and clock control circuits comprise; control registers which hold control data for controlling the stop and supply of power and clocks to the plurality of the controlled circuits, and control logics which respectively input the control data in the control registers and an instruction signal to the forcible release control circuit to thereby control the supply and stop of the power and clocks to the controlled circuits, and wherein each of the control logics; allows the power and clocks to be supplied when the control data indicates the supply of the power and clocks, allows the power and clocks to stop when the control data indicates the stop of the power and clocks and the power and clock request signal indicates no request for the supply of the power and clocks, and allows the power and clocks to be supplied when the control data indicates the stop of the power and clocks and the power and clock request signal requests the supply of the power and clocks.
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13. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which respectively control the stop and supply of the power and clocks to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks, conducted on one or more predetermined controlled circuits by the power and clock control circuits only during a period required by a power and clock request signal received at a first external input terminal of the semiconductor device; wherein the predetermined controlled circuit comprises a slave interface circuit which is slave-interface operated with respect to an external device which functions as a requesting circuit and produces the power and clock request signal received at the first external input terminal. - View Dependent Claims (14, 15)
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16. A semiconductor device comprising:
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a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which respectively control the stop and supply of the power and clocks to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks, conducted on one or more predetermined controlled circuits by the power and clock control circuits only during a period required by a power and clock request signal received at a first external input terminal of the semiconductor device; wherein the one or more predetermined controlled circuits comprise a first controlled circuit controlled from the outside of the semiconductor device and a second controlled circuit controlled by the first controlled circuit; wherein the first controlled circuit comprises a slave interface circuit which is slave-interface operated by an external data processing device coupled to the first external input terminal, and wherein the second controlled circuit comprises a memory interface circuit controlled by the slave interface circuit and the central processing unit. - View Dependent Claims (17, 18)
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19. The
A semiconductor device comprising: -
a central processing unit for controlling a stop and supply of power and clocks, and for executing instructions; a plurality of controlled circuits subject to control of the stop and supply of the power and clocks; power and clock control circuits which respectively control the stop and supply of the power and clocks to the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases the supply and stop of the power and clocks, conducted on one or more predetermined controlled circuits by the power and clock control circuits only during a period required by a power and clock request signal received at a first external input terminal of the semiconductor device; wherein the one or more predetermined controlled circuits comprise a first controlled circuit controlled from the outside of the semiconductor device and a second controlled circuit controlled by the first controlled circuit; wherein the first controlled circuit comprises a slave interface circuit which is slave-interface operated by an external data processing device coupled to the first external input terminal, and wherein the second controlled circuit comprises an internal memory controlled by the slave interface circuit and the central processing unit. - View Dependent Claims (20, 21)
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22. A semiconductor device comprising:
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a central processing unit for controlling a setting and release of a low power consumption state, and for executing instructions; a plurality of controlled circuits each subject to control of a setting and release of a low power consumption state; a low power consumption control circuit which controls the setting and release of the low power consumption state to and from the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases a low power consumption state set to a predetermined controlled circuit by the low power consumption control circuit only during a period required by a request signal outputted from a requesting circuit, to thereby temporarily resume power to said predetermined controlled circuit and thus enable operation of at least one resource required by the requesting circuit.
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23. A semiconductor device comprising:
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a central processing unit for controlling a setting and release of a low power consumption state, and for executing instructions; a plurality of controlled circuits each subject to control of a setting and release of a low power consumption state; a low power consumption control circuit which controls the setting and release of the low power consumption state to and from the central processing unit and the controlled circuits, based on execution of one or more instructions by the central processing unit; and a forcible release control circuit which forcibly releases a low power consumption state set to a predetermined controlled circuit by the low power consumption control circuit only during a period required by a request signal received at a first external input terminal, to thereby temporarily resume power to said predetermined controlled circuit and thus enable operation of at least one resource required by an external circuit issuing said request signal.
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24. A semiconductor device comprising:
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a central processing unit (CPU) configured to execute instructions and capable of entering a low power consumption state in response to one or more of said instructions; a plurality of controlled circuits, each capable of being placed in a low power consumption state in response to one or more of said instructions; a forcible release control circuit configured to; receive a request signal from a requesting circuit; and in response to the request signal and only during a period required by the request signal, release a first low power consumption state of a predetermined one of said plurality of controlled circuits which has been placed in the first low power consumption state by the CPU, so that the requesting circuit is able to use said predetermined one of said plurality of controlled circuits; and an interrupt controller configured to; receive an interrupt request from said requesting circuit; and in response to the interrupt request, output at least one signal to restore the CPU to an operable state from a second low power consumption state of the CPU. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A semiconductor device comprising:
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a requesting circuit configured to output a first request signal; a central processing unit (CPU) configured to execute instructions and selectively occupy a low power consumption state; a plurality of controlled circuits, each configured to selectively occupy a low power consumption state; a forcible release control circuit configured to; receive the first request signal from the requesting circuit; and in response to the first request signal, release a low power consumption state of a first controlled circuit assembly comprising one or more controlled circuits so that the requesting circuit is capable of accessing said first controlled circuit assembly; and an interrupt controller configured to; receive an interrupt request from said requesting circuit; and in response to the interrupt request, output at least one signal to restore the CPU to an operable state from a low power consumption state of the CPU; wherein; following receipt of the interrupt request, a low power consumption state of a second controlled circuit assembly is released, the second controlled circuit assembly comprising one or more controlled circuits, at least one of which is different from the one or more controlled circuits belonging to the first controlled circuit assembly; and in the operable state, the CPU is capable of accessing the second controlled circuit assembly. - View Dependent Claims (35, 36, 37, 38, 39, 40)
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Specification