Memory devices and method for error test, recordation and repair

• US 8,499,207 B2
• Filed: 07/27/2012
• Issued: 07/30/2013
• Est. Priority Date: 06/17/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mohr, Christian N., Cowles, Timothy B.
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US13/559,942
• Publication Number:
  US 20120297257A1
• Time in Patent Office: 368 Days
• Field of Search: None
• US Class Current: 714/710
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/838 with substitution of defective spares

Abstract

In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Claims

1. A memory device, comprising:

an array of memory cells including a plurality of redundant memory cells for replacing memory cells of the array; and

an on-die device operably coupled with the array of memory cells and configured to store data associated with unavailability of a redundant memory cell, wherein the on-die device includes an anti-fuse bank configured to indicate the unavailability of the redundant memory cell with at least one blown anti-fuse and at least one non-blown anti-fuse of the anti-fuse bank.

2. The memory device of claim 1, wherein the at least one blown anti-fuse corresponds to an address of an unavailable redundant memory cell, and wherein the at least one non-blown anti-fuse corresponds to an enable redundancy circuit of the redundant memory cell.

3. The memory device of claim 1, wherein the data includes an indication that the redundant memory cell is a failed redundant memory cell.

4. A memory device, comprising:

an array of memory cells including a plurality of redundant memory cells for replacing memory cells of the array; and

an on-die device operably coupled with the array of memory cells and configured to store data associated with unavailability of a redundant memory cell, wherein the data includes at least one bit associated with an address of the redundant memory cell and at least one bit associated with an enable of the redundant memory cell.

5. A memory device, comprising:

an array of memory cells including a plurality of redundant memory cells for replacing memory cells of the array; and

an on-die device operably coupled with the array of memory cells and configured to store data associated with unavailability of a redundant memory cell, wherein the data includes at least one bit associated with which test the redundant memory cell failed.

6. The memory device of claim 5, wherein the on-die device includes a device selected from the group consisting of a fuse, a switching device, and an on-die register.

7. A memory device, comprising:

a memory array on a semiconductor die;

a plurality of programmable devices on the semiconductor die associated with a plurality of redundant memory cells; and

control circuitry operably coupled with the memory array and the plurality of programmable devices, the control circuitry configured to refrain from using a particular redundant memory cell of the plurality of redundant memory cells when an associated programmable device indicates the particular redundant memory cell of the plurality to be unavailable, wherein the associated programmable device includes;

a first programmable device corresponding to at least a portion of a memory address of a particular redundant memory cell; and

a second programmable device corresponding to enablement of the particular redundant memory cell.

8. The memory device of claim 7, wherein an indication that the particular redundant memory cell is unavailable includes:

the first programmable device being programmed; and

the second programmable device being unprogrammed.

9. The memory device of claim 8, wherein the plurality of programmable devices includes a bank of anti-fuses.

10. The memory device of claim 9, wherein:

the first programmable device being programmed includes a blown anti-fuse; and

the second programmable device being unprogrammed includes an anti-fuse that is not blown.

11. The memory device of claim 7, wherein the associated programmable device is configured to indicate that the particular redundant memory cell is a failed redundant memory cell.

12. The memory device of claim 7, further comprising a detection circuit on the semiconductor die configured to read data from the plurality of programmable devices to determine which of the plurality of redundant memory cells is unavailable.

13. The memory device of claim 7, wherein the plurality of programmable devices includes at least one register on the semiconductor die.

14. The memory device of claim 13, wherein the at least one register is further configured to store data associated with at least one failed main memory cell of the memory array.

15. A method, comprising signifying unavailability of a redundant memory cell of a memory array with an on-die device for replacement of a main memory cell of the memory array, wherein signifying unavailability of the redundant memory cell includes blowing at least one anti-fuse in a redundancy circuit while maintaining an anti-fuse of an enable redundancy circuit.

16. The method of claim 15, wherein signifying unavailability of the redundant memory cell further includes limiting the unavailability of the redundant memory cell for non-repair purposes, while being available for repair purposes.

17. The method of claim 15, wherein maintaining the anti-fuse of the enable redundancy circuit includes retaining the integrity of the anti-fuse of the enable redundancy circuit.

22. The method of claim 15, further comprising:

detecting the unavailability of the redundant memory cell; and

refraining from using the redundant memory cell for replacement of the main memory cell.

23. The method of claim 22, wherein detecting the unavailability of the redundant memory cell is performed by an on-die detection circuit.

24. The method of claim 22, wherein detecting the unavailability of the redundant memory cell is performed by an off-die detection circuit.

18. A method, comprising signifying unavailability of a redundant memory cell of a memory array with an on-die device for replacement of a main memory cell of the memory, wherein signifying unavailability of the redundant memory cell includes blowing at least one anti-fuse corresponding to an address bit of the redundant memory cell without blowing an anti-fuse corresponding to an enable bit of the redundant memory cell.

19. The method of claim 18, wherein blowing the at least one anti-fuse is performed by a test device.

20. A method. comprising:

signifying unavailability of a redundant memory cell of a memory array with an on-die device for replacement of a main memory cell of the memory;

a first testing of a plurality of redundant memory cells for identifying a failed redundant memory cell prior to complete packaging; and

retaining a result of the testing in the on-die device for subsequent testing that occurs at a later fabrication stage than a fabrication stage of the first testing.

21. The method of claim 20, wherein the subsequent testing occurs after complete packaging.