Race logic synthesis for large-scale integrated circuit designs

• US 8,499,266 B2
• Filed: 06/23/2011
• Issued: 07/30/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Terence Wai-Kwok Chan
• Original Assignee: Terence Wai-Kwok Chan
• Inventors: Chan, Terence Wai-Kwok
• Primary Examiner(s): Do, Thuan
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US13/167,237
• Publication Number:
  US 20120005638A1
• Time in Patent Office: 768 Days
• Field of Search: 716104-109
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) and/or ESL (electronic system level) design source files of an IC design are compiled into a common design database. Race logic analysis is performed on the IC design, either by a third-party tool or by the same EDA (electronic design automation) tool that also performing race logic synthesis, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the common design database, and getting rid of all identified race logic in the IC design. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free common design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer. Another aspect of the invention is outputting the re-synthesized logic in the common design database to new HDL/ESL source files. User may use these revised source files to analyze the IC design using other third-party EDA design/verification tools.

Claims

1. A computer implemented method of performing race logic synthesis on an integrated circuit (IC) design, comprising:

(a) Compiling by computer, an IC design source files, coded in any one or a combination of HDL (hardware description language) and/or ESL (electronic system level) design languages, into a design data base;

(b) Performing static and/or dynamic race logic analysis of the IC design, either by a host application, or by an external race logic audit tool, or the combination of both;

(c) Determining the execution order of process blocks of the IC design in the design database, either using the default process block execution order by the host application or obtaining that order from user;

(d) Executing the race logic synthesis functions to get rid of all race logic, as detected in (b), in the compiled IC design database;

(e) As a user-specified option or a default action of the host application, generating updated HDL/ESL source files for the IC design, where race logic has been remedied by the race logic synthesis functions in (d),

wherein step d comprises;

(f) analyzing all circuit signals and registers in the IC design that have been determined to be involved in concurrent assignment race logic, and re-synthesizing the driving process blocks of these signals and registers, to eliminate the race logic while retaining the original logic functions of the IC design;

(g) analyzing all circuit signals and registers in the IC design that have been determined to be involved in concurrent assignment and reference race logic, and re-synthesizing the driving and driven process blocks of these signals and registers, to eliminate the race logic while retaining the original logic functions of the IC design;

(h) analyzing all process blocks in the IC design that have been determined to be involved in concurrent invocation race via user- and/or system-defined functions/tasks, and re-synthesizing them to eliminate the concurrent invocation race logic while retaining the original logic functions of the IC design.

2. A computer implemented method of performing race logic synthesis on an integrated circuit (IC) design, comprising:

(a) compiling by computer, an IC design source files, coded in any one or a combination of HDL (hardware description language) and/or ESL (electronic system level) design languages, into a design data base;

(b) performing static and/or dynamic race logic analysis of the IC design, either by a host application, or by an external race logic audit tool, or the combination of both;

(c) determining the execution order of process blocks of the IC design in the design database, either using the default process block execution order by the host application or obtaining that order from user;

(d) executing the race logic synthesis functions to get rid of all race logic, as detected in (b), in the compiled IC design database;

(e) as a user-specified option or a default action of the host application, generating updated HDL/ESL source files for the IC design, where race logic has been remedied by the race logic synthesis functions in (d);

(f) For each signal or register object that has been identified as having concurrent assignment race issue, as in step (b), if there are only two driving process blocks for the register or signal object, and they all use blocking (non-blocking) assignment to drive the signal or register object, and at least one of them does not reference the signal or register object'"'"'s value, then replacing all the assignments in that process block for the signal or register object to be non-blocking (blocking), which imposes a deterministic assignment order by the two process blocks for the signal or register object, and hence resolving the concurrent assignment race logic;

(g) If step (f) is not applicable for a signal or register object that is identified as having concurrent assignment race issue, collecting the driving factors for each driving process block of the signal or register object;

(h) Collecting all driving process blocks of the signal or register object that have one or more driving factors that are compatible;

(i) Replacing all driving process blocks that have compatible driving factors by one single driving process block to impose a deterministic assignment order to the signal or register object in the merged driving process block;

(j) As an alternative to (i), if every driving process block of a register or signal object always assigns to the object and then reads values from that object, and the register or signal object is not being referenced in other part of the IC design, then the register or signal object can be duplicated in each of its driving process blocks, with no change to the driving process blocks'"'"' logic, to eliminate concurrent assignment race logic to the register or signal object; and

(k) As another alternative to (i), if a signal or register is driven by multiple drivers, via process blocks and/or concurrent assignment statements, that drive non-overlapping bits of the signal or register, then replace all those drivers into a single driving concurrent assignment statement or a process block, where the signal or register is driven by the concatenation of all the driving expressions of those former drivers, in the order corresponding to the bit order of the signal or register that those former drivers drive.

3. The method of claim 2 wherein the operation of (g) further comprises the step of collecting the driving factors for each driving process block of a signal or register object, wherein the driving factors comprise:

triggering signals to the process block;

a trigger event type;

possible delays in assigning a new state to the signal or register;

the assignment type;

possible enabling conditions which control the assignment event; and

an assigned new state value or driving signals and/or registers.

4. The method of claim 2 wherein the operation of (h) further comprises checking if any two sets of driving factors for two driving process blocks of a signal or register object are compatible simultaneously, wherein the two sets of driving factors are compatible if they contains one or more the same trigger signals that are triggered with compatible event types, and the signal or register object could be assigned with different logic values, with the same assignment type, at the same time when the triggered signals are active.

5. The method of claim 4 wherein the trigger event types of a trigger signal in two driving factors are compatible if they are of the same event type (positive-edge, negative-edge or any-edge), one is positive-edge and the other is any-edge, or one is negative-edge and the other is any-edge.

6. The method of claim 4 wherein the assignment types in two driving factors are compatible if they are both blocking assignment type or both non-blocking assignment type.

7. The method of claim 2 wherein the operation of (i) further comprises replacing all the driving process blocks that are found to have compatible driving factors by a new driving process block, wherein the new driving process block will contain all the HDL/ESL code of the replaced driving process blocks, and the new driving process block will be triggered by a single driving factors.

8. The method of claim 7 further comprising the step of creating new driving factors for the newly created driving process block for a signal or register object, wherein the new driving factors will contain the union of all the triggered signals in the driving factors of the replaced process blocks, and if the trigger event types of a trigger signal in the replaced driving factors are the same (e.g., all are positive-edge trigger, all are negative-edge trigger, or all are any-edge trigger), then using the same trigger event type for the trigger signal in the new driving factors, and if the trigger event types of a trigger signal in the replaced driving factors are not the same, then using the any-edge trigger event type for the trigger signal in the new driving factors.

9. The method of claim 7 further comprising the step of merging all HDL/ESL code of the replaced driving process blocks into a new driving process block further comprising determining the order of the replaced driving process blocks that are specified in the HDL/ESL source files, and the orders of process block execution in step (c) and if the order of execution of process blocks is the same as they are specified in the HDL/ESL source files, the merged driving process block contains the HDL/ESL code of the replaced process blocks, in the same order as they are specified in the HDL/ESL source files, and if the execution of process blocks are in the reverse order as specified in the HDL/ESL source files, then the merged driving process block contains the HDL/ESL code of the replaced process blocks, in the reverse order as those process blocks are specified in the HDL/ESL source files.

10. The method of claim 9 further comprises comprising the step of adding a controlling expression for the HDL/ESL code from a replaced process block when the code is copied to the merged driving process block when a replaced driving process block is triggered by a positive-edge (or negative-edge) of a trigger signal, wherein the merged process block is triggered by the any-edge of that trigger signal, wherein the controlling condition consists of the trigger signal'"'"'s value equals logic ‘

1’

(or trigger signal'"'"'s value equal logic ‘

0’

) for the copied HDL/ESL code to be executed when the merged driving process block is active, and if there are multiple trigger signals in the controlling condition, the trigger signals'"'"' asserted states are logically OR'"'"'ed together to form a new controlling expression.

11. A computer implemented method of performing race logic synthesis on an integrated circuit (IC) design, comprising:

(a) compiling by computer, an IC design source files, coded in any one or a combination of HDL (hardware description language) and/or ESL (electronic system level) design languages, into a design data base;

(b) performing static and/or dynamic race logic analysis of the IC design, either by a host application, or by an external race logic audit tool, or the combination of both;

(c) determining the execution order of process blocks of the IC design in the design database, either using the default process block execution order by the host application or obtaining that order from user;

(d) executing the race logic synthesis functions to get rid of all race logic, as detected in (b), in the compiled IC design database;

(e) as a user-specified option or a default action of the host application, generating updated HDL/ESL source files for the IC design, where race logic has been remedied by the race logic synthesis functions in (d);

(f) For each signal or register object that is identified as involved in concurrent assignment and reference race logic, according to step (b), changing all assignments in all the driving process blocks for the target signal or register object to be non-blocking assignments, if all the driving process blocks are coded in design languages that support non-blocking assignments, and all the driving process blocks do not reference the signal or register object'"'"'s values;

(g) If the conditions set forth in (f) cannot be applied, examining the signal or register object that is identified as having concurrent assignment and reference race issue, and collecting the driving factors for each driving (source) process block and for each driven (sink) process block of the signal or register object;

(h) Collecting all driving and driven process blocks of the signal or register object that have one or more driving factors that are compatible; and

(i) Replacing all driving and driven process blocks that have compatible driving factors by one process block, so as to impose a deterministic assignment and reference order of the signal or register object in the merged process block.

12. The method of claim 11 wherein the operation of (g) further comprises collecting the driving factors for each driving and driven process block of a signal or register object, wherein the driving factors comprise:

triggering signals to the process block;

a trigger event type;

possible delays in assigning a new state to or referencing the value of the signal or register object;

the assignment type;

possible enabling conditions which control the assignment or reference event.

13. The method of claim 11 wherein the operation of (h) further comprises checking if any two sets of driving factors for a driving process block and a driven process block of a signal or register object are compatible simultaneously, wherein the two sets of driving factors are compatible if they contains one or more the same trigger signals that are triggered with compatible event types, and the signal or register object could be assigned with a new value and be referenced at the same time, and the assignment type is a blocking assignment, when the triggered signals are active.

14. The method of claim 13 wherein the trigger event types of a trigger signal in two driving factors are compatible if they are the same event type (positive-edge, negative-edge or any-edge), one is positive-edge and the other is any-edge, or one is negative-edge and the other is any-edge.

15. The method of claim 11 wherein the operation of (i) further comprises replacing all the driving and driven process blocks that are found to have compatible driving factors by a new merged process block that contains all the HDL/ESL code of the replaced driving and driven process blocks, and the new process block is triggered by a single driving factors.

16. The method of claim 15 further comprising the step of creating new driving factors for the newly created process block for a signal or register object that contains all triggered signals in the driving factors of the replaced process blocks, and if the trigger event types of a trigger signal in the replaced driving factors are the same, then using the same trigger event type for the trigger signal in the new driving factors, if the trigger event types of a trigger signal in the replaced driving factors are not the same, then using the any-edge trigger event type for the trigger signal in the new driving factors.

17. The method of claim 15 further comprising the step of merging all HDL/ESL code of the replaced driving and driven process blocks into the new merged process block further comprising determining the order of the replaced driving and driven process blocks that are specified in the HDL/ESL source files, and the order of process block execution as obtained in step (c), and if the order of execution of process blocks is the same as they are specified in the HDL/ESL source files, the merged process block will contained the HDL/ESL code of the replaced driving and driven process blocks, in the same order as those process blocks are specified in the HDL/ESL source files, and if the execution of process blocks are in the reverse order as they are specified in the HDL/ESL source files, then the merged process block contains the HDL/ESL code of the replaced driving and driven process blocks, in the reverse order as those process blocks are specified in the HDL/ESL source files.

18. The method of claim 17 further comprising the step of adding a controlling expression for the HDL/ESL code from a replaced process block when the code is copied to the merged process block when a replaced driving or driven process block is triggered by a positive-edge (or negative-edge) of a trigger signal, wherein the merged process block is triggered by the any-edge of that trigger signal, wherein the controlling condition consists of the trigger signal'"'"'s value equals logic ‘

1’

(or trigger signal'"'"'s value equals logic ‘

0’

) in order for the copied HDL/ESL code to be executed when the merged process block is active, and if there are multiple trigger signals in a controlling condition, the trigger signals'"'"' asserted states are logically OR'"'"'ed together to form a new controlling expression.

19. A computer implemented method of performing race logic synthesis on an integrated circuit (IC) design, comprising:

(a) compiling by computer, an IC design source files, coded in any one or a combination of HDL (hardware description language) and/or ESL (electronic system level) design languages, into a design data base;

(b) performing static and/or dynamic race logic analysis of the IC design, either by a host application, or by an external race logic audit tool, or the combination of both;

(c) determining the execution order of process blocks of the IC design in the design database, either using the default process block execution order by the host application or obtaining that order from user;

(d) executing the race logic synthesis functions to get rid of all race logic, as detected in (b), in the compiled IC design database;

(e) as a user-specified option or a default action of the host application, generating updated HDL/ESL source files for the IC design, where race logic has been remedied by the race logic synthesis functions in (d);

(f) Examining each user- or system-defined function or task that is identified, as according to step (b), as having concurrent invocation race issue, and collecting the driving factors for each process block that invoke the function or task;

(g) Collecting all process blocks for the function or task that have one or more driving factors that are compatible; and

(h) Replacing all those process blocks that have compatible driving factors by one process block, so as to impose a deterministic invocation order of the function or task in the merged process block.

20. The method of claim 19 wherein the operation of (f) further comprises collecting the driving factors for each process block of the function or task, wherein the driving factors comprise:

triggering signals to the process block;

a trigger event type;

possible delays in invocation of the function or task;

possible enabling conditions which control the invocation event.

21. The method of claim 19 wherein the operation of (g) further comprises checking if any two sets of driving factors for two process blocks of the function or task are compatible simultaneously, wherein two sets of driving factors are compatible if they contains one or more the same trigger signals that are triggered with compatible event types, and the function or task could be invoked in those two process blocks at the same time, when the triggered signals are active.

22. The method of claim 21 wherein the trigger event types of a trigger signal in two driving factors are compatible if they are the same event type (positive-edge, negative-edge or any-edge), one is positive-edge and the other is any-edge, or one is negative-edge and the other is any-edge.

23. The method of claim 19 wherein the operation of (h) further comprises replacing all the process blocks that are found to have compatible driving factors by a new merged process block, wherein the new process block will contain all the HDL/ESL code of the replaced process blocks, and the new process block will be triggered by a single driving factors.

24. The method of claim 23 further comprises comprising the step of creating new driving factors for the newly created process block for a function or task, wherein the new driving factors contains all the triggered signals in the driving factors of the replaced process blocks and if the trigger event types of a trigger signal in the replaced driving factors are the same, then using the same trigger event type for the trigger signal in the new driving factors. However, if the trigger event types of a trigger signal in the replaced driving factors are not the same, then using the any-edge trigger event type for the trigger signal in the new driving factors.

25. The method of claim 23 further comprising the step of merging all HDL/ESL code of the replaced process blocks into the new merged process block by determining the order of appearance of the replaced process blocks as specified in the HDL/ESL source files, and the order of process blocks execution as in step (c), and if the order of execution of process blocks is the same as they are specified in the HDL/ESL source files, the merged process block contains the HDL/ESL code of the replaced process blocks, in the same order as those process blocks are specified in the HDL/ESL source files and, if the execution of process blocks are in the reverse order as they are specified in the HDL/ESL source files, then the merged process block contains the HDL/ESL code of the replaced process blocks, in the reverse order as those process blocks are specified in the HDL/ESL source files.

26. The method of claim 25 further comprising the step of adding a controlling expression for the HDL/ESL code from a replaced process block when the code is copied to the merged process block when a replaced process block is triggered by a positive-edge (or negative-edge) of a trigger signal, wherein the merged process block is triggered by the any-edge of that trigger signal, wherein the controlling condition will consist of the trigger signal'"'"'s value equals logic ‘

1’

(or trigger signal'"'"'s value equals logic ‘

0’

) in order for the copied HDL/ESL code to be executed when the merged process block is active, wherein if there are multiple trigger signals in a controlling condition, the trigger signals'"'"' asserted states are logically OR'"'"'ed together to form a new controlling expression.

27. A computer implemented method of performing race logic synthesis on an integrated circuit (IC) design, comprising:

(a) compiling by computer, an IC design source files, coded in any one or a combination of HDL (hardware description language) and/or ESL (electronic system level) design languages, into a design data base;

(b) performing static and/or dynamic race logic analysis of the IC design, either by a host application, or by an external race logic audit tool, or the combination of both;

(c) determining the execution order of process blocks of the IC design in the design database, either using the default process block execution order by the host application or obtaining that order from user;

(d) executing the race logic synthesis functions to get rid of all race logic, as detected in (b), in the compiled IC design database;

(e) as a user-specified option or a default action of the host application, generating updated HDL/ESL source files for the IC design, where race logic has been remedied by the race logic synthesis functions in (d);

wherein step (e) further comprises writing out race logic synthesized IC design logic to new HDL/ESL source files by;

(f) Obtaining user input to select the generation of update HDL/ESL files for the re-synthesized logic and if the user input is negative, no updated HDL/ESL source files is generated;

(g) For each event block in an IC design database, recording the block'"'"'s source file path name, the start and end line numbers of that event block in the source file, and the input and output signals and registers that are connected to the event block;

(h) Creating new HDL/ESL source files that contain the merged process blocks that eliminate the concurrent assignment race of signals and registers, concurrent assignment and reference race of signals and registers, and concurrent invocation race of user- and system-defined functions/tasks;

(i) Naming all the updated HDL/ESL source files with the same names as their original file names, but with a new file name extension or alternatively renaming all original HDL/ESL source files that contains the replaced process blocks with different names, and naming all updated HDL/ESL files as generated in (f) with corresponding original file names.

28. The method of claim 27 wherein step (h) further comprises for each HDL/ESL source file that contains replaced process blocks, deleting the original process blocks, except one in the updated HDL/ESL file.

29. The method of claim 28 further comprising replacing the un-deleted process block by a newly created merged process block, in the same design module as the replaced process block and if the new process block is being driven or drives signals and/or registers that are not connected to the design module that hosts the new process block, replacing those driven and driving signals and/or registers by their hierarchical full path names, wherein the design module containing the merged process block and other (un-modified) design modules in the same source file are written out to the updated HDL/ESL source file.