Timing exact design conversions from FPGA to ASIC
First Claim
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1. A device comprising a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC), wherein a design implemented in either the FPGA or the ASIC comprises equivalent timing, the device comprised of:
- a programmable logic circuit having corresponding layouts in the FPGA and the ASIC, wherein the device is selectably fabricated as the FPGA or the ASIC; and
a random access memory (RAM) element to program the logic circuit in the FPGA; and
a read only memory (ROM) conductive element to program the logic circuit in the ASIC, wherein the RAM element is duplicated to the ROM element to equivalently program the programmable logic circuit.
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Abstract
A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.
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Citations
10 Claims
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1. A device comprising a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC), wherein a design implemented in either the FPGA or the ASIC comprises equivalent timing, the device comprised of:
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a programmable logic circuit having corresponding layouts in the FPGA and the ASIC, wherein the device is selectably fabricated as the FPGA or the ASIC; and a random access memory (RAM) element to program the logic circuit in the FPGA; and a read only memory (ROM) conductive element to program the logic circuit in the ASIC, wherein the RAM element is duplicated to the ROM element to equivalently program the programmable logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification