Methods of forming micro-electromechanical resonators using passive compensation techniques

• US 8,501,515 B1
• Filed: 02/25/2011
• Issued: 08/06/2013
• Est. Priority Date: 02/25/2011
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Pan, Wanling
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/035,148
• Time in Patent Office: 893 Days
• Field of Search: 438/48, 438/406, 438/455, 438/458, 438/459, 438/476, 438/694, 438/700, 257/E27.006
• US Class Current: 438/48
• CPC Class Codes: H03H 2003/0407 Temperature coefficient
• CPC Class Codes: H03H 2003/0478 in a process for mass production
• CPC Class Codes: H03H 3/02 for the manufacture of piezoelectric or electrostrictive resonators or networks H03H3/08 takes precedence
• CPC Class Codes: H03H 9/02228 Guided bulk acoustic wave devices or Lamb wave devices having interdigital transducers situated in parallel planes on either side of a piezoelectric layer
• CPC Class Codes: H03H 9/172 Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
• CPC Class Codes: H03H 9/564 implemented with thin-film techniques

Abstract

Methods of forming electro-micromechanical resonators provide passive temperature compensation of semiconductor device layers used therein. A first substrate is provided that includes a first electrically insulating temperature compensation layer on a first semiconductor device layer. A step is performed to bond the first electrically insulating temperature compensation layer to a second substrate containing the second electrically insulating temperature compensation layer therein, to thereby form a relatively thick temperature compensation layer. A piezoelectric layer is formed on the first electrically insulating temperature compensation layer and at least a first electrode is formed on the piezoelectric layer.

Claims

1. A method of forming a micro-electromechanical resonator, comprising:

forming a first substrate comprising a first buried insulating layer, a first semiconductor device layer on the first buried insulating layer and a first electrically insulating temperature compensation layer on the first semiconductor device layer;

forming a second substrate comprising a second buried insulating layer, a second semiconductor device layer on the second buried insulating layer and a second electrically insulating temperature compensation layer on the second semiconductor device layer;

bonding the second electrically insulating temperature compensation layer directly to the first electrically insulating temperature compensation layer;

then

removing the second buried insulating layer to thereby expose the second semiconductor device layer;

forming a bottom electrode on the second semiconductor device layer;

forming a piezoelectric layer on the bottom electrode and on first and second electrically insulating temperature compensation layers;

forming at least a first electrode on the piezoelectric layer, which extends between the first electrode and the bottom electrode;

selectively etching the piezoelectric layer, the second semiconductor device layer, the first and second electrically insulating temperature compensation layers and the first semiconductor device layer in sequence to expose the first buried insulating layer; and

removing at least portion of the buried insulating layer from the first semiconductor device layer to thereby define a suspended resonator body comprising first portions of the piezoelectric layer, the first and second second semiconductor device layers and the first and second electrically insulating temperature compensation layers, which extend between the first semiconductor device layer and the second semiconductor device layer.

2. The method of claim 1, wherein said bonding comprises fusion bonding the second electrically insulating temperature compensation layer directly to the first electrically insulating temperature compensation layer.

3. The method of claim 1, wherein said bonding comprises fusion bonding the second electrically insulating temperature compensation layer directly to the first electrically insulating temperature compensation layer at a temperature of about 1000°

C.

4. The method of claim 1, wherein the first and second semiconductor device layers are silicon device layers;

wherein the first and second electrically insulating temperature compensation layers are silicon dioxide layers; and

wherein a combined thickness of the first and second electrically insulating temperature compensation layers is sufficient to provide substantially complete temperature compensation to the first and second semiconductor device layers.