Self-aligned protection layer for copper post structure

• US 8,501,616 B2
• Filed: 10/25/2012
• Issued: 08/06/2013
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Yu, Chen-Hua
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US13/660,348
• Publication Number:
  US 20130049194A1
• Time in Patent Office: 285 Days
• Field of Search: 438/612, 438/613
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A semiconductor device including a semiconductor substrate and a conductive post overlying and electrically connected to the substrate. The semiconductor device further includes a manganese-containing protection layer on a surface of the conductive post. A method of forming a semiconductor device. The method includes forming a bond pad region on a semiconductor substrate. The method further includes forming a conductive post overlying and electrically connected to the bond pad region. The method further includes forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn).

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a conductive post overlying and electrically connected to the substrate; and

a manganese-containing protection layer on a surface of the conductive post.

2. The semiconductor device of claim 1, wherein the manganese-containing protection layer is a self-aligned protection layer.

3. The semiconductor device of claim 1, further comprising a conductive region formed in the substrate configured to electrically connect the substrate to the conductive post.

4. The semiconductor device of claim 3, further comprising a post-passivation interconnect line configured to electrically connect the conductive region and the conductive post.

5. The semiconductor device of claim 1, further comprising an under bump metallurgy (UBM) layer between the substrate and the conductive post.

6. The semiconductor device of claim 5, wherein the manganese-containing protection layer covers sidewalls of the conductive post and sidewalls of the UBM layer.

18. The semiconductor device of claim 1, further comprising a copper alloy layer between the substrate and the conductive post.

19. The semiconductor device of claim 18, wherein the copper alloy layer includes a gradient manganese concentration.

7. A method of forming a semiconductor device, the method comprising:

forming a bond pad region on a semiconductor substrate;

forming a conductive post overlying and electrically connected to the bond pad region; and

forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn).

8. The method of claim 7, wherein forming the conductive post comprises forming the conductive post containing an alloy comprising manganese.

9. The method of claim 8, wherein forming the protection layer comprises annealing the alloy conductive post to diffuse the manganese in the alloy conductive post to the surface of the conductive post.

10. The method of claim 9, wherein annealing the alloy conductive post comprises annealing the alloy conductive post in an environment containing at least one of NH₃ or N₂, and the protection layer comprises manganese nitride.

11. The method of claim 9, wherein forming the conductive post comprises forming a copper-manganese alloy post, and annealing the copper-manganese alloy conductive post comprises reducing copper oxide and forming manganese oxide.

12. The method of claim 7, further comprising forming a post-passivation interconnect line to electrically connect the conductive post to the bond pad.

13. The method of claim 7, further comprising forming an under bump metallurgy (UBM) layer between the bond pad and the conductive post, wherein the protection layer covers sidewalls of the conductive post and the UBM layer.

20. The method of claim 7, further comprising forming a copper alloy layer between the bond pad region and the conductive post.

14. A method of forming a semiconductor device, the method comprising:

forming a bond pad region on a semiconductor substrate;

forming a conductive post overlying and electrically connected to the bond pad region, the conductive post comprising a copper-manganese alloy; and

forming a manganese-containing protection layer on sidewalls of the conductive post.

15. The method of claim 14, wherein forming the manganese-containing protection layer comprises annealing the copper-manganese alloy of the conductive post.

16. The method of claim 15, wherein annealing the copper-manganese alloy comprises annealing the copper-manganese alloy in an environment containing at least one of NH₃ or N₂, to form a self-aligned manganese nitride protection layer.

17. The method of claim 14, further comprising forming the manganese-containing protection layer over a top surface of the conductive post.