Methods of fabricating isolation regions of semiconductor devices and structures thereof

• US 8,501,632 B2
• Filed: 12/20/2005
• Issued: 08/06/2013
• Est. Priority Date: 12/20/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Stapelmann, Chris, Tilke, Armin
• Primary Examiner(s): Hoffberg, Robert J
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US11/312,878
• Publication Number:
  US 20070141852A1
• Time in Patent Office: 2,786 Days
• Field of Search: 257/510, 257/E21.549, 438/758
• US Class Current: 438/758
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming at least one trench in a semiconductor substrate having a top surface, the at least one trench comprising sidewalls and a bottom surface;

forming an oxide liner on the sidewalls and the bottom surface of the at least one trench, wherein the oxide liner is formed directly on the semiconductor substrate;

forming a nitride liner directly on the oxide liner and over the top surface of the semiconductor substrate using atomic layer deposition (ALD), the nitride liner having a thickness of about 3 Å

to about 25 Å

;

treating the nitride liner, wherein treating the nitride liner comprises treating the nitride liner with a plasma process, a heat process, a UV process, or combinations thereof, in order to alter a tensile or compressive stress; and

completely filling the at least one trench in a single process with an insulating material directly on the nitride liner.

2. The method according to claim 1, further comprising removing a portion of the insulating material from over the top surface of the semiconductor substrate, wherein after removing the portion of insulating material from over the top surface of the semiconductor substrate, the oxide liner, the nitride liner and a remaining portion of the insulating material in the at least one trench are coplanar with the top surface of the semiconductor substrate, and wherein the oxide liner, the nitride liner and the remaining portion of the insulating material form an isolation region of the semiconductor device.

3. The method according to claim 1, wherein using atomic layer deposition (ALD) comprises performing a first Si-forming cycle and then performing an N-forming cycle.

4. A method of fabricating a semiconductor device, the method comprising:

forming at least one trench in a semiconductor substrate having a top surface, the at least one trench comprising sidewalls and a bottom surface;

forming an oxide liner on the sidewalls and the bottom surface of the at least one trench, wherein the oxide liner is formed directly on the semiconductor substrate;

forming a nitride liner directly on the oxide liner and over the top surface of the semiconductor substrate using atomic layer deposition (ALD), wherein forming the nitride liner comprises forming Si₃N₄, Si_xN_y, or Si₃N₄ or Si_xN_y combined with about 1% or less of hydrogen, and wherein the nitride liner comprises a thickness of about 3 Å

to about 25 Å

;

treating the nitride liner, wherein treating the nitride liner comprises treating the nitride liner with a plasma process, a heat process, a UV process, or combinations thereof, in order to alter a tensile or compressive stress; and

completely filling the at least one trench in a single process with an insulating material directly on the nitride liner.

5. The method according to claim 4, further comprising forming a sacrificial material layer over the semiconductor substrate before forming the at least one trench in the semiconductor substrate, wherein forming the at least one trench in the semiconductor substrate further comprises forming the at least one trench in the sacrificial material layer, wherein forming the nitride liner further comprises forming the nitride liner over sidewalls of the sacrificial material layer and over a top surface of the sacrificial material layer, and further comprising removing at least a portion of the sacrificial material layer, after filling the at least one trench with the insulating material.

6. The method according to claim 4, further comprising removing a portion of the insulating material from over the top surface of the semiconductor substrate, wherein after removing the portion of the insulating material from over the top surface of the semiconductor substrate, the oxide liner, the nitride liner, and a remaining portion of the insulating material in the at least one trench are coplanar with the top surface of the semiconductor substrate, and wherein the oxide liner, the nitride liner and the remaining portion of the insulating material form an isolation region of the semiconductor device.

7. The method according to claim 4, wherein using atomic layer deposition (ALD) comprises performing a first Si-forming cycle and then performing an N-forming cycle.

8. A method of forming an isolation region of a semiconductor device, the method comprising:

forming a pad oxide over a top surface of a semiconductor substrate;

forming a pad nitride over the pad oxide;

forming at least one trench in the pad nitride, the pad oxide, and the semiconductor substrate;

forming an oxide liner over at least a portion of the at least one trench formed in the semiconductor substrate, wherein the oxide liner is formed directly on the semiconductor substrate;

forming a nitride liner over the at least one trench and directly on the oxide liner using atomic layer deposition (ALD), the nitride liner having a thickness of about 25 Angstroms or less;

treating the nitride liner with a process to increase a tensile stress of the nitride liner, wherein the process comprises a plasma process, a heat process, a UV process, or combinations thereof, after forming the nitride liner;

after treating the nitride liner, completely filling the at least one trench in a single process with an oxide material, wherein the oxide material is directly disposed on the nitride liner;

removing a first portion of the oxide material, the pad oxide and the pad nitride; and

wherein after removing the first portion of the oxide material, the pad oxide and the pad nitride, the oxide liner, the nitride liner, and a second portion of the oxide material are coplanar with the top surface of the semiconductor substrate, and wherein the nitride liner, the oxide liner, and the second portion of the oxide material form the isolation region of the semiconductor device.

9. The method according to claim 8, wherein forming the pad nitride and the nitride liner comprise forming silicon nitride, and wherein forming the pad oxide, the oxide liner, and the oxide material comprise forming silicon dioxide.

10. The method according to claim 8, further comprising forming at least two active areas in the semiconductor substrate, wherein forming the at least one trench comprises forming a trench between the at least two active areas, and wherein depositing the oxide material comprises forming a shallow trench isolation (STI) region between the at least two active areas.

11. The method according to claim 8, further comprising forming at least two active areas in the semiconductor substrate, wherein forming the at least one trench comprises forming a trench between the at least two active areas, wherein depositing the oxide material comprises forming a shallow trench isolation (STI) region between the at least two active areas, and wherein treating the nitride liner improves a performance of the active areas.

12. A method of forming an isolation region of a semiconductor device, the method comprising:

forming a sacrificial material layer over a top surface of a semiconductor substrate;

forming at least one trench in the sacrificial material layer and the semiconductor substrate, the at least one trench comprising sidewalls and a bottom surface;

forming an oxide liner over at least the sidewalls and the bottom surface of the at least one trench in the semiconductor substrate, wherein the oxide liner is formed directly on the semiconductor substrate;

forming an ultra thin nitride liner over at least the oxide liner using atomic layer deposition (ALD), the ultra thin nitride liner being continuous and having a thickness of about 25 Angstroms or less;

treating the ultra thin nitride liner with a treatment to increase a stress of the ultra thin nitride liner, wherein the treatment comprises a UV treatment between about 400-550°

C.; and

after treating the ultra thin nitride liner, depositing an oxide material directly on the ultra thin nitride liner to completely fill the at least one trench in a single process.

13. The method according to claim 12, wherein forming the ultra thin nitride liner comprises forming the ultra thin nitride liner using rapid ALD.

14. The method according to claim 12, wherein at least a portion of the sacrificial material layer comprises a pad nitride layer comprising silicon nitride, wherein forming the ultra thin nitride liner comprises forming silicon nitride, and wherein removing at least the portion of the sacrificial material from over the semiconductor substrate comprises removing the pad nitride layer.

15. The method according to claim 12, wherein at least a portion of the sacrificial material layer comprises a pad oxide layer comprising silicon dioxide, wherein forming the oxide liner comprises forming silicon dioxide, and wherein filling the at least one trench with the oxide material comprises filling the trench with silicon dioxide.

16. The method according to claim 12, further comprising

removing at least a portion of the sacrificial material layer from over the semiconductor substrate;

and

removing the portion of the oxide material from over the top surface of the semiconductor substrate, wherein after removing the portion of the oxide material from over the top surface of the semiconductor substrate, the oxide liner, the ultra thin nitride liner and a remaining portion of the oxide material are coplanar with the top surface of the semiconductor substrate.

17. The method according to claim 12, wherein using atomic layer deposition (ALD) comprises performing a first Si-forming cycle and then performing an N-forming cycle.