Array substrate for display device and method of fabricating the same

• US 8,502,229 B2
• Filed: 03/09/2012
• Issued: 08/06/2013
• Est. Priority Date: 06/03/2009
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Yong-Yub, Ryoo, Chang-Il
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): NGUYEN, CUONG B
• Application Number:
  US13/416,972
• Publication Number:
  US 20120211746A1
• Time in Patent Office: 515 Days
• Field of Search: 438149-151, 438/30, 438158-159, 257/E51.005, 257/E29.151, 257/57, 257/59, 257/66, 257/72, 257/359, 257/390, 257/443, 257/E21.411, 257/E21.412, 257/E27.1, 257/E29.117, 349/43
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.

Claims

1. An array substrate, comprising:

a substrate having a pixel region;

a gate electrode on the substrate;

a gate insulating layer on the gate electrode;

an oxide semiconductor layer on the gate insulating layer;

an auxiliary pattern on the oxide semiconductor layer, the auxiliary pattern having a same shape as the oxide semiconductor layer;

source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, said exposed portion of the auxiliary pattern covering an entire channel region of the oxide semiconductor layer and including a metal oxide;

a data line over the gate insulating layer, the data line connected to the source electrode;

a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode; and

a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.

2. The array substrate of claim 1, wherein the metal oxide over the channel region includes titanium oxide.

3. The array substrate of claim 2, wherein unexposed portions of the auxiliary pattern include one of titanium and titanium alloy.

4. The array substrate of claim 1, wherein the oxide semiconductor layer includes one of amorphous indium gallium zinc oxide (a-IGZO) and zinc tin oxide (ZTO).

5. The array substrate of claim 1, wherein the oxide semiconductor layer has a thickness of about 500 Å

to about 1000 Å

, and the auxiliary pattern has a thickness of about 50 Å

to about 500 Å

.

6. The array substrate of claim 1, further comprising:

first and second dummy patterns between the data line and the gate insulating layer.

7. The array substrate of claim 6, wherein the first dummy pattern has a same material and a same layer as the oxide semiconductor layer, and the second dummy pattern has a same material and a same layer as other portions unexposed portions of the auxiliary pattern.