Capacitor, semiconductor device and manufacturing method thereof

• US 8,502,232 B2
• Filed: 03/14/2008
• Issued: 08/06/2013
• Est. Priority Date: 05/14/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Murakami, Satoshi, Hirakata, Yoshiharu, Fujimoto, Etsuko, Yamazaki, Yu, Yamazaki, Shunpei
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US12/077,161
• Publication Number:
  US 20080174710A1
• Time in Patent Office: 1,971 Days
• Field of Search: 257/49, 257/52, 257/57, 257/59, 257/66, 257/72, 257/E27.13, 257/E27.131
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.

Claims

1. A semiconductor device comprising:

a first substrate;

a thin film transistor over the first substrate, comprising a wiring electrically connected to an active layer of the thin film transistor;

an interlayer insulating film over the wiring, having a contact hole;

a pixel electrode over the interlayer insulating film, electrically connected to the wiring via the contact hole;

a conductive layer over the interlayer insulating film adjacent to the pixel electrode with an insulating layer therebetween;

a spacer over the interlayer insulating film; and

a second substrate over the spacer,

wherein the spacer overlaps the contact hole.

2. The semiconductor device according to claim 1,

wherein the spacer is formed into a tapered shape.

3. The semiconductor device according to claim 1,

wherein the insulating layer has a hole which is filled with an insulating material comprising the resin material.

4. The semiconductor device according to claim 1,

wherein the active layer comprises polycrystalline silicon.

5. The semiconductor device according to claim 1,

wherein the conductive layer is set at a constant electric potential.

6. The semiconductor device according to claim 1,

wherein the insulating layer comprises at least one metal element included in the conductive layer.

7. The semiconductor device according to claim 1, further comprising:

a first alignment film over and in contact with the spacer;

a second alignment film adjacent to the second substrate; and

a liquid crystal between the first alignment film and the second alignment film,

wherein the spacer comprises a resin material.

8. A semiconductor device comprising:

a first substrate;

a thin film transistor over the first substrate, comprising an active layer comprising a channel forming region;

an interlayer insulating film over the thin film transistor, having a contact hole;

a pixel electrode over the interlayer insulating film, electrically connected to the active layer via the contact hole;

a conductive layer adjacent to the pixel electrode with an insulating layer therebetween;

a spacer over the interlayer insulating film, comprising a resin material; and

a second substrate over the spacer,

wherein the spacer overlaps the contact hole, and

wherein the conductive layer at least partly overlaps the channel forming region.

9. The semiconductor device according to claim 8,

wherein the spacer is formed into a tapered shape.

10. The semiconductor device according to claim 8,

wherein the insulating layer has a hole which is filled with an insulating material comprising the resin material.

11. The semiconductor device according to claim 8,

wherein the active layer comprises polycrystalline silicon.

12. The semiconductor device according to claim 8,

wherein the conductive layer is set at a constant electric potential.

13. The semiconductor device according to claim 8,

wherein the insulating layer comprises at least one metal element included in the conductive layer.

14. The semiconductor device according to claim 8, further comprising:

a first alignment film over and in contact with the spacer;

a second alignment film adjacent to the second substrate; and

a liquid crystal between the first alignment film and the second alignment film.

15. A semiconductor device comprising:

a first substrate;

a thin film transistor over the first substrate, comprising an active layer comprising a channel forming region;

a first interlayer insulating film over the thin film transistor, having a first contact hole;

a second interlayer insulating film over the first interlayer insulating film, having a second contact hole;

a pixel electrode over the second interlayer insulating film, electrically connected to the active layer via the first contact hole and the second contact hole;

a conductive layer adjacent to the pixel electrode with an insulating layer therebetween;

a spacer over the second interlayer insulating film, comprising a resin material; and

a second substrate over the spacer,

wherein the spacer overlaps the second contact hole, and

wherein the conductive layer at least partly overlaps the channel forming region.

16. The semiconductor device according to claim 15,

wherein the spacer is formed into a tapered shape.

17. The semiconductor device according to claim 15,

wherein the insulating layer has a hole which is filled with an insulating material comprising the resin material.

18. The semiconductor device according to claim 15,

wherein the active layer comprises polycrystalline silicon.

19. The semiconductor device according to claim 15,

wherein the conductive layer is set at a constant electric potential.

20. The semiconductor device according to claim 15,

wherein the insulating layer comprises at least one metal element included in the conductive layer.

21. The semiconductor device according to claim 15, further comprising:

a first alignment film over and in contact with the spacer;

a second alignment film adjacent to the second substrate; and

a liquid crystal between the first alignment film and the second alignment film.

22. A semiconductor device comprising:

a first substrate;

a thin film transistor over the first substrate, comprising an active layer comprising a channel forming region;

a first interlayer insulating film over the thin film transistor, having a first contact hole;

a wiring over the first interlayer insulating film, electrically connected to the active layer via the first contact hole;

a second interlayer insulating film over the first interlayer insulating film, having a second contact hole;

a pixel electrode over the second interlayer insulating film, electrically connected to the wiring via the second contact hole;

a conductive layer adjacent to the pixel electrode with an insulating layer therebetween;

a spacer over the second interlayer insulating film, comprising a resin material; and

a second substrate over the spacer,

wherein the spacer overlaps the second contact hole, and

wherein the conductive layer at least partly overlaps the channel forming region.

23. The semiconductor device according to claim 22,

wherein the spacer is formed into a tapered shape.

24. The semiconductor device according to claim 22,

wherein the insulating layer has a hole which is filled with an insulating material comprising the resin material.

25. The semiconductor device according to claim 22,

wherein the active layer comprises polycrystalline silicon.

26. The semiconductor device according to claim 22,

wherein the conductive layer is set at a constant electric potential.

27. The semiconductor device according to claim 22,

wherein the insulating layer comprises at least one metal element included in the conductive layer.

28. The semiconductor device according to claim 22, further comprising:

a first alignment film over and in contact with the spacer;

a second alignment film adjacent to the second substrate; and

a liquid crystal between the first alignment film and the second alignment film.

29. A semiconductor device comprising:

a first substrate;

a thin film transistor over the first substrate, comprising a wiring electrically connected to an active layer of the thin film transistor;

an interlayer insulating film over the wiring, having a contact hole;

a conductive layer over the interlayer insulating film;

a pixel electrode over the conductive layer with an insulating layer therebetween, electrically connected to the wiring via the contact hole;

a spacer over the interlayer insulating film, comprising a resin material; and

a second substrate over the spacer,

wherein the spacer overlaps the contact hole.

30. The semiconductor device according to claim 29,

wherein the spacer is formed into a tapered shape.

31. The semiconductor device according to claim 29,

wherein the insulating layer has a hole which is filled with an insulating material comprising the resin material.

32. The semiconductor device according to claim 29,

wherein the active layer comprises polycrystalline silicon.

33. The semiconductor device according to claim 29,

wherein the conductive layer is set at a constant electric potential.

34. The semiconductor device according to claim 29,

wherein the insulating layer comprises at least one metal element included in the conductive layer.

35. The semiconductor device according to claim 29, further comprising:

a first alignment film over and in contact with the spacer;

a second alignment film adjacent to the second substrate; and

a liquid crystal between the first alignment film and the second alignment film.