Semiconductor device with memory cells

• US 8,502,292 B2
• Filed: 07/14/2011
• Issued: 08/06/2013
• Est. Priority Date: 07/16/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Matsuzaki, Takanori, Nagatsuka, Shuhei, Inoue, Hiroki
• Primary Examiner(s): Coleman, William D
• Application Number:
  US13/182,488
• Publication Number:
  US 20120012845A1
• Time in Patent Office: 754 Days
• Field of Search: 257/300, 257/351
• US Class Current: 257/300
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device with a novel structure is provided, which can hold stored data even when no power is supplied and which has no limitations on the number of writing operations. A semiconductor device is formed using a material which enables off-state current of a transistor to be reduced significantly; e.g., an oxide semiconductor material which is a wide-gap semiconductor. With use of a semiconductor material which enables off-state current of a transistor to be reduced significantly, the semiconductor device can hold data for a long period. In a semiconductor device with a memory cell array, parasitic capacitances generated in the nodes of the first to the m-th memory cells connected in series are substantially equal, whereby the semiconductor device can operate stably.

Claims

1. A semiconductor device comprising m (m is an integer of 2 or more) write word lines, m read word lines, a bit line, a source line, a signal line and a first to an m-th memory cells connected in series between the bit line and the source line,

the first to the m-th memory cells each comprising:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode and a first channel formation region;

a second transistor including a second gate electrode, a second source electrode, a second drain electrode and a second channel formation region; and

a capacitor,

wherein the first channel foil cation region includes a semiconductor material different from a semiconductor material of the second channel formation region,

wherein in each of the first to the m-th memory cells, the first gate electrode, either the second source electrode or the second drain electrode, and one electrode of the capacitor are electrically connected to form a node of which electric charges are held, and

wherein a parasitic capacitance of the node included in the m-th memory cell is half of or more than half of a parasitic capacitance of the node included in an i (i is an integer of from 1 to (m−

1))-th memory cell.

2. The semiconductor device according to claim 1, wherein the first channel formation region includes silicon, and the second channel formation region includes an oxide semiconductor.

3. A semiconductor device comprising m (m is an integer of 2 or more) write word lines, m read word lines, a bit line, a source line, a signal line and a first to an m-th memory cells connected in series between the bit line and the source line,

the first to the m-th memory cells each comprising:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode and a first channel formation region;

a second transistor including a second gate electrode, a second source electrode, a second drain electrode and a second channel formation region; and

a capacitor,

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region,

wherein in each of the first to the m-th memory cells, the first gate electrode, either the second source electrode or the second drain electrode, and one electrode of the capacitor are electrically connected to form a node of which electric charges are held, and

wherein parasitic capacitances of the nodes included in the first to the m-th memory cells are substantially equal.

4. The semiconductor device according to claim 3, wherein the first channel formation region includes silicon, and the second channel formation region includes an oxide semiconductor.

5. A semiconductor device comprising m (m is an integer of 2 or more) write word lines, m read word lines, a bit line, a source line, a signal line and a first to an m-th memory cells connected in series between the bit line and the source line,

the first to the m-th memory cells each comprising:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode and a first channel formation region;

a second transistor including a second gate electrode, a second source electrode, a second drain electrode and a second channel formation region; and

a capacitor,

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region,

wherein the second transistor overlaps with at least a part of the first transistor with an insulating layer therebetween,

wherein either the second source electrode or the second drain electrode is over and in contact with the first gate electrode,

wherein either the second source electrode or the second drain electrode includes a first region in contact with the first gate electrode, a second region extending from the first gate electrode toward the second channel formation region, and a third region extending from the gate electrode in a direction opposite to the second channel formation region, and

wherein a parasitic capacitance between the third region and the first transistor in the m-th memory cell is substantially equal to a parasitic capacitance between the third region and the first transistor in an i (i is an integer of from 1 to (m−

1))-th memory cell.

6. The semiconductor device according to claim 5, wherein lengths in a channel length direction of the second source electrodes in the first to the m-th memory cells are equal.

7. The semiconductor device according to claim 5,

the second source electrode in the m-th memory cell further comprising:

a fourth region, which is a part of the second region and overlaps with the second gate electrode, and

a fifth region, which is a part of the third region and overlaps with the source line,

wherein a parasitic capacitance between the fifth region and the source line is substantially equal to a parasitic capacitance between the second source electrode in the (m−

1)-th memory cell and the second gate electrode in the m-th memory cell.

8. The semiconductor device according to claim 7, wherein a length in a channel length direction of the fifth region is equal to a length in a channel length direction of a region where the second source electrode in the (m−

1)-th memory cell overlaps with the second gate electrode of the m-th memory cell.

9. The semiconductor device according to claim 5, wherein the first channel formation region includes silicon, and the second channel formation region includes an oxide semiconductor.