Semiconductor device and method for manufacturing same

• US 8,502,305 B2
• Filed: 03/15/2012
• Issued: 08/06/2013
• Est. Priority Date: 09/21/2011
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohta, Tsuyoshi, Yasuhara, Norio, Arai, Masatoshi, Kawano, Takahiro, Nishiwaki, Tatsuya
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/421,816
• Publication Number:
  US 20130069147A1
• Time in Patent Office: 509 Days
• Field of Search: 257/244, 257/274, 257/594, 257/E21.042, 257/E21.044, 257/E21.045, 257/E21.056, 257/E21.06, 257/E21.369, 257/E21.4
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductive type;

a base region of a second conductive type provided on the semiconductor layer;

a first contact region of a second conductive type provided on the base region;

a gate electrode provided via a gate insulating film in a trench piercing through the first contact region and the base region and reaching the semiconductor layer;

an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element;

a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region;

a first major electrode electrically connected to the semiconductor layer; and

a second major electrode provided on the interlayer insulating film and connected to the source region and the first contact region.

2. The device according to claim 1,

wherein a first conductive type impurity element contained in the source region is the same as the first impurity element contained in the interlayer insulating film.

3. The device according to claim 1,

wherein a distance between an upper end of the source region and a back surface of the semiconductor layer is longer than a distance between an upper face of the gate electrode and the back surface of the semiconductor layer.

4. The device according to claim 1, further comprising:

a field plate electrode provided below the gate electrode in the trench, the field plate electrode facing the semiconductor layer via a field insulating film.

5. The device according to claim 4, comprising:

a plurality of the trenches piercing through the first contact region and the base region,

wherein the base region is sandwiched between a pair of the adjacent trenches, and the base region is wider than a minimum width of the semiconductor layer between the pair of the adjacent trench.

6. The device according to claim 1,

wherein a distance between a lower end of the source region and the back surface of the semiconductor layer is shorter than a distance between a lower end of the first contact region and the back surface of the semiconductor layer.

7. The device according to claim 1,

wherein an upper face of the interlayer insulating film, an upper end of the source region, and an upper face of the first contact region are flush with each other.

8. The device according to claim 1,

wherein a concentration of a second conductive type impurity contained in the first contact region is lower than a concentration of a first conductive type impurity contained in the source region.

9. The device according to claim 1,

wherein the gate electrode is electrically connected to the second major electrode.

10. The device according to claim 1, further comprising:

a second contact region of a second conductive type connected to the first contact region,

wherein the second contact region extends from the first contact region to the semiconductor layer side, and

a distance between a lower end of the second contact region and the back surface of the semiconductor layer is shorter than a distance between a lower end of the source region and the back surface of the semiconductor layer.

11. The device according to claim 10,

wherein the distance between the lower end of the second contact region and the back surface of the semiconductor layer is shorter than a distance between a lower end of the base region and the back surface of the semiconductor layer.

12. The device according to claim 10,

wherein the distance between the lower end of the second contact region and the back surface of the semiconductor layer is the same as the distance between the lower end of the base region and the back surface of the semiconductor layer.

13. The device according to claim 10,

wherein the distance between the lower end of the second contact region and the back surface of the semiconductor layer is longer than the distance between the lower end of the base region and the back surface of the semiconductor layer.

14. The device according to claim 10,

wherein a concentration of a second conductive type impurity contained in the second contact region is lower than a concentration of a second conductive type impurity contained in the first contact region and higher than a concentration of a second conductive type impurity contained in the base region.