Semiconductor device and production method thereof

• US 8,502,319 B2
• Filed: 12/20/2010
• Issued: 08/06/2013
• Est. Priority Date: 12/21/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takeda, Hiroshi
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US12/973,261
• Publication Number:
  US 20110147815A1
• Time in Patent Office: 960 Days
• Field of Search: None
• US Class Current: 257/368
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a first horizontal layer comprised of a semiconductor substrate, a channel region formed therein, and a source/drain diffusion layer region provided adjacent to the channel region and having impurities implanted therein;

a second horizontal layer, formed on top of the first horizontal layer, the second horizontal layer comprised of a gate insulating film formed over a top of the semiconductor substrate and a gate electrode formed over the gate insulating film,

the gate electrode having opposite-facing sidewalls running in a direction away from the top of the semiconductor substrate to a top of the gate electrode;

gate sidewall insulating films respectively formed adjacent to the sidewalls of the gate electrode in the second horizontal layer;

a plurality of protrusion portions that protrude from the source/drain diffusion layer region into the second horizontal layer, each protrusion portion having a curved side surface that faces toward a side portion of a respective gate sidewall insulating film, an interstice formed between each gate sidewall insulating film and a respective side surface of the protrusion portions; and

a stress applying film formed over the source/drain diffusion layer region except over an upper part of the gate electrode, the stress applying film filling the interstices between the protrusion portions and the gate sidewall insulating films,

wherein the plurality of protrusion portions comprise bottom portions in the second horizontal layer and a plurality of top extending parts that extend vertically from the bottom portions,

the top extending parts being vertically aligned with each other and spaced from one another, and each spaced from one another by an interstice.

2. The semiconductor device according to claim 1, wherein the plurality of protrusions are formed such that interstices are not provided directly between the source/drain diffusion layer region and the gate sidewall insulating films.

3. The semiconductor device according to claim 1, wherein respective bottom portions of the protrusion portions are adjacent to bottom portions of the gate sidewall insulating films such that the interstices do not directly contact the source/drain diffusion layer region.

4. The semiconductor device according to claim 1, wherein the plurality of protrusion portions comprises a material having a stronger adhesiveness with the semiconductor substrate than that of the stress applying film.

5. The semiconductor device according to claim 1, wherein the curved side surfaces of the protrusion portions curve downward from respective top portions of the protrusion portions to respective bottoms of the gate sidewall insulating films.

6. The semiconductor device according to claim 1, wherein the interstices formed by the curved side surfaces of the protrusion portions and the respective gate sidewall insulating films each have a V-shape.