Through-substrate via waveguides

• US 8,502,338 B2
• Filed: 09/09/2010
• Issued: 08/06/2013
• Est. Priority Date: 09/09/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Hu, Hsien-Pin, Kuo, Chin-Wei, Liu, Sally
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US12/878,803
• Publication Number:
  US 20120061795A1
• Time in Patent Office: 1,062 Days
• Field of Search: 257/503, 257/508, 257/520, 257/698, 257/774, 257/E23.067, 257/E23.144, 257/E23.174
• US Class Current: 257/508
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13027 the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0296 involving a specific disposition of the protective devices
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.

Claims

1. A device comprising:

a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface;

a through-substrate via (TSV) extending from the first surface to the second surface of the semiconductor substrate; and

a well region of a second conductivity type opposite the first conductivity type encircling the TSV, wherein the well region extends from the first surface to the second surface of the semiconductor substrate.

2. The device of claim 1 further comprising an isolation layer encircling the TSV, wherein the well region encircles and contacts the isolation layer.

3. The device of claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type, and wherein the well region is an n-well region.

4. The device of claim 3, wherein the n-well region and the semiconductor substrate form a diode of an electro-static discharge (ESD) circuit, and wherein the n-well region is connected to a signal input pad of the ESD circuit, and the semiconductor substrate is connected to a VSS node of the ESD circuit.

5. The device of claim 1 further comprising:

a heavily doped region of the first conductivity type in the semiconductor substrate, wherein a distance between the heavily doped region and the well region is less than about 1 μ

m; and

a capacitor coupled to the heavily doped region.

6. A device comprising:

a p-type semiconductor substrate;

a through-substrate via (TSV) in the p-type semiconductor substrate;

an isolation layer encircling the TSV; and

an n-well region encircling the isolation layer, wherein the n-well region is between and contacting the isolation layer and the p-type semiconductor substrate, and wherein an entirety of the isolation layer is physically spaced apart from the p-type semiconductor substrate.

7. The device of claim 6, wherein the p-type semiconductor substrate comprises a first side and a second side opposite the first side, and wherein each of the TSV, the isolation layer, and the n-well region extends from the first side to the second side of the semiconductor substrate.

8. The device of claim 6, wherein the n-well region and the p-type semiconductor substrate form a diode of an electro-static discharge (ESD) circuit, and wherein the n-well region is connected to a signal input pad of the ESD circuit, and the p-type semiconductor substrate is connected to a VSS node of the ESD circuit.

9. The device of claim 6 further comprising:

a heavily doped p-type region in the p-type semiconductor substrate, wherein a distance between the heavily doped p-type region and the n-well region is less than about 1 μ

m; and

a capacitor coupled to the heavily doped p-type region.

10. A device comprising:

a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface;

a through-substrate via (TSV) extending from the first surface to the second surface of the semiconductor substrate; and

a well region of a second conductivity type opposite the first conductivity type encircling the TSV, wherein the well region extends from the first surface to the second surface of the semiconductor substrate;

a heavily doped region of the first conductivity type in the semiconductor substrate, wherein a distance between the heavily doped region and the well region is less than about 1 μ

m; and

a capacitor coupled to the heavily doped region.

11. The device of claim 10, wherein the well region and the semiconductor substrate form a diode of an electro-static discharge (ESD) circuit, and wherein the well region is connected to a signal input pad of the ESD circuit, and the semiconductor substrate is connected to a VSS node of the ESD circuit.