Through-wafer interconnects for photoimager and memory wafers

• US 8,502,353 B2
• Filed: 06/07/2011
• Issued: 08/06/2013
• Est. Priority Date: 09/02/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Watkins, Charles M., Hiatt, William M., Hembree, David R., Wark, James M., Farnworth, Warren M., Tuttle, Mark E., Rigg, Sidney B., Oliver, Steven D., Kirby, Kyle K., Wood, Alan G., Velicky, Lu
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US13/154,550
• Publication Number:
  US 20110233777A1
• Time in Patent Office: 791 Days
• Field of Search: 438/667
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Claims

1. A microelectronic device comprising:

a substrate having a generally planar frontside surface opposite a backside surface;

a bond pad carried by the substrate proximate to the frontside surface; and

an interconnect extending through the substrate and electrically coupled to the bond pad, the interconnect comprising—

a hole extending from the frontside surface to the backside surface, the hole extending through the bond pad;

a dielectric material disposed on a sidewall of the hole;

a first conductive material disposed on the dielectric material and contacting at least a portion of the bond pad; and

a second conductive material disposed on the first conductive material and electrically coupled to the bond pad via the first conductive material, wherein the second conductive material is co-planar or recessed with reference to the frontside surface.

2. The microelectronic device of claim 1, further comprising a conductive member at the backside surface of the substrate, wherein the conductive member is electrically coupled to the bond pad via the interconnect.

3. The microelectronic device of claim 2 wherein the conductive member is a solder ball.

4. The microelectronic device of claim 1 wherein the second conductive material fills the hole and extends from the frontside surface to the backside surface.

5. The microelectronic device of claim 1 wherein the dielectric material is disposed on at least a portion of the bond pad.

6. The microelectronic device of claim 1 wherein the substrate comprises one or more passivation layers.

7. A microelectronic device comprising:

a substrate having a first side opposite a second side, wherein the first side of the substrate is substantially flat;

a bond pad at the first side of the substrate; and

an interconnect coupled to the bond pad and extending through the substrate from the first side to the second side, the interconnect comprising—

a via passing through the bond pad, the via having a sidewall extending from the first side to the second side;

a dielectric deposited on the sidewall of the via;

a first conductor deposited on the dielectric, wherein the first conductor is electrically coupled to the bond pad; and

a second conductor deposited on the first conductor and electrically coupled to the bond pad through the first conductor, wherein the second conductor is co-planar or recessed with reference to the first side of the substrate.

8. The microelectronic device of claim 7 wherein the second conductor is surrounded by a dielectric passivation layer at the first side of the substrate.

9. The microelectronic device of claim 7, further comprising a conductive ball at the second side of the substrate, wherein the conductive ball is electrically coupled to the bond pad through the interconnect.

10. The microelectronic device of claim 7 wherein the second conductive material fills a hole and extends from the first side of the substrate to the second side.

11. The microelectronic device of claim 7 wherein the first conductor contacts a top portion of the bond pad adjacent to the first side of the substrate.