3-D integrated circuit lateral heat dissipation

• US 8,502,373 B2
• Filed: 05/05/2008
• Issued: 08/06/2013
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kaskoun, Kenneth, Gu, Shiqun, Nowak, Matthew
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/115,076
• Publication Number:
  US 20090273068A1
• Time in Patent Office: 1,919 Days
• Field of Search: 257/692, 257/705, 257/706, 257/712, 438/122
• US Class Current: 257/712
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01019 Potassium [K]

Abstract

By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.

Claims

1. A three dimensional integrated circuit (IC) device, comprising:

a first die stacked on a second die, each die comprising an active face and a substrate, the dies'"'"' active faces coupled together by a plurality of tier to tier connections, and the tier to tier connections creating a gap between the active laces of the first and second die;

a through-substrate via filled with a first thermally conductive material disposed in the first die; and

a thermally conductive layer positioned within the gap.

2. The three dimensional integrated circuit (IC) device of claim 1 wherein a thermal conductivity of the first thermally conductive material is at least 10 W/m/K.

3. The three dimensional integrated circuit (IC) device of claim 1 wherein the first thermally conductive material is electrically insulating.

4. The three dimensional integrated circuit (IC) device of claim 1 wherein the first thermally conductive material is a patterned film.

5. The three dimensional integrated circuit (IC) device of claim 1 further comprising:

a second thermally conductive material disposed at an end of at least one of the die, the second thermally conductive material being thermally coupled to the first thermally conductive material disposed in the first die.

6. The three dimensional integrated circuit (IC) device of claim 1 wherein the thermally conductive layer is selected from a list of diamond matrix and diamond film pattern.

7. The three dimensional integrated circuit (IC) device of claim 1 in which the first thermally conductive material is comprised at least partially of carbon nanotubes.

8. The three dimensional integrated circuit (IC) device of claim 1 in which the first die is circumferentially larger than the second die.

9. The three dimensional integrated circuit (IC) device of claim 8 in which the second die comprises at least two dies, at least one of the two dies further comprising a second thermally conductive layer.

10. The three dimensional integrated circuit (IC) device of claim 1 wherein the thermally conductive layer is deposited by one of CVD, PVD, spin on, and screen on.

11. A three dimensional integrated circuit (IC) device, comprising:

a first die and a second die, each die comprising an active face and a substrate;

means for coupling the dies'"'"' active faces, the means for coupling creating a gap between the first die and second die;

means, disposed in a via extending through the first die, for conducting heat; and

means disposed within the gap, for conducting heat.

12. The three dimensional integrated circuit (IC) device of claim 11 wherein

the means disposed within the gap is selected from a list of diamond matrix and diamond film pattern.

13. The three dimensional integrated circuit (IC) device of claim 11 wherein the means disposed in a via extending through the first die consists of carbon nanotubes.

14. A three dimensional integrated circuit (IC) device, comprising:

a first die stacked on a second die, the first die being circumferentially larger than the second die;

the first and second dies coupled together by a plurality of tier to tier connections, and the tier to tier connections creating a gap between the first and second die;

a through-substrate via filled with a thermally conductive material disposed in the first die; and

the second die comprising a thermally conductive layer.

15. The three dimensional integrated circuit (IC) device of claim 14 in which the second die comprises at least two dies, at least one of the two dies further comprising a second thermally conductive layer.

16. An integrated circuit (IC) device, comprising:

a first die comprising an active layer on a substrate,

a through-substrate via filled with a thermally conductive material disposed in the first die; and

a thermally conductive and electrically insulating layer directly coupled to only the active layer of the first die distal from the substrate.

17. The integrated circuit (IC) device of claim 16 wherein a thermal conductivity of the thermally conductive material is at least 10 W/m/K.

18. The integrated circuit (IC) device of claim 16 wherein the thermally conductive material is electrically insulating.

19. The integrated circuit (IC) device of claim 16 wherein the thermally conductive material is a patterned film.

20. The integrated circuit (IC) device of claim 16 further comprising:

a second die having an active layer on a substrate;

the first and the second die coupled together by a plurality of tier to tier connections, the tier to tier connections creating a gap between the first and second die; and

the thermally conductive and electrically insulating layer provided within the gap.

21. The integrated circuit (IC) device of claim 16 wherein the thermally conductive and electrically insulating layer is selected from a list of diamond matrix and diamond film pattern.

22. The circuit (IC) device of claim 20 in which the first die is circumferentially larger than the second die.

23. The integrated circuit (IC) device of claim 16 wherein the thermally conductive and electrically insulating layer is deposited, by one of CVD, PVD, spin on, and screen on.

24. The integrated circuit (IC) device of claim 16 wherein the thermally conductive material is electrically conductive.

25. The circuit (IC) device of claim 24 in which the thermally conductive material is comprised at least partially of carbon nanotubes.