Delay lines, methods for delaying a signal, and delay lock loops
First Claim
1. A phase inverter, comprising:
- an odd number of first inverters coupled in series between a first input and a first output, the odd number of first inverters having a collective propagation delay from the first input to the first output that is equal to a first delay value; and
an even number of second inverters coupled in series between a second input and a second output, the second input being isolated from the first input, the even number of second inverters having a collective propagation delay from the second input to the second output that is equal to a second delay value, the second delay value being substantially equal to the first delay value.
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Accused Products
Abstract
Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.
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Citations
20 Claims
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1. A phase inverter, comprising:
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an odd number of first inverters coupled in series between a first input and a first output, the odd number of first inverters having a collective propagation delay from the first input to the first output that is equal to a first delay value; and an even number of second inverters coupled in series between a second input and a second output, the second input being isolated from the first input, the even number of second inverters having a collective propagation delay from the second input to the second output that is equal to a second delay value, the second delay value being substantially equal to the first delay value. - View Dependent Claims (2, 3, 4, 5)
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6. A phase inverter, comprising:
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a first path configured to receive a first signal at a first input and to provide a first phase shifted signal by phase shifting the first signal based on a first propagation delay of the first path, wherein the first phase shifted signal is inverted relative to the first signal; and a second path configured to receive a second signal at a second input and to provide a second phase shifted signal at an output by phase shifting the second signal based on a second propagation delay of the second path, wherein the first propagation delay is substantially equal to the second propagation delay. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A phase inverter, comprising:
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an odd plurality of serially coupled inverters configured to delay and invert a first signal based on a first propagation delay of the odd plurality of serially coupled inverters; and an even plurality of serially coupled inverters configured to delay a second signal based on a second propagation delay of the even plurality of serially coupled inverters, wherein the first propagation delay is approximately equal to the second propagation delay. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification