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Delay lines, methods for delaying a signal, and delay lock loops

  • US 8,502,579 B2
  • Filed: 01/04/2013
  • Issued: 08/06/2013
  • Est. Priority Date: 01/21/2009
  • Status: Active Grant
First Claim
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1. A phase inverter, comprising:

  • an odd number of first inverters coupled in series between a first input and a first output, the odd number of first inverters having a collective propagation delay from the first input to the first output that is equal to a first delay value; and

    an even number of second inverters coupled in series between a second input and a second output, the second input being isolated from the first input, the even number of second inverters having a collective propagation delay from the second input to the second output that is equal to a second delay value, the second delay value being substantially equal to the first delay value.

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