Battery state monitoring circuit and battery device
First Claim
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1. A battery state monitoring circuit, comprising:
- a first reference voltage circuit;
a first voltage comparator circuit for comparing a reference voltage of the first reference voltage circuit and a voltage at an overcurrent detection terminal;
a power supply voltage detection circuit which is provided between two power supply voltage terminals, for detecting an abrupt decrease in a power supply voltage;
a first PMOS transistor including a gate connected to an output terminal of the first voltage comparator circuit;
a second PMOS transistor including a gate connected to an output terminal of the power supply voltage detection circuit;
a first delay circuit which is connected to a drain of the first PMOS transistor;
a second delay circuit which is connected to a drain of the second PMOS transistor; and
a control circuit which is connected to an output terminal of the first delay circuit and an output terminal of the second delay circuit.
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Abstract
Provided is a battery state monitoring circuit which detects that a voltage of a secondary battery has decreased abruptly because of an overcurrent, thereby being capable of protecting a battery device from an abrupt decrease in voltage of the secondary battery caused by the overcurrent. The battery state monitoring circuit includes a voltage comparator circuit and a power supply voltage detection circuit for detecting an abrupt decrease in power supply voltage, in which the voltage comparator circuit detects a normal overcurrent while the power supply voltage detection circuit detects the abrupt decrease in power supply voltage caused by load short-circuit.
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Citations
7 Claims
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1. A battery state monitoring circuit, comprising:
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a first reference voltage circuit; a first voltage comparator circuit for comparing a reference voltage of the first reference voltage circuit and a voltage at an overcurrent detection terminal; a power supply voltage detection circuit which is provided between two power supply voltage terminals, for detecting an abrupt decrease in a power supply voltage; a first PMOS transistor including a gate connected to an output terminal of the first voltage comparator circuit; a second PMOS transistor including a gate connected to an output terminal of the power supply voltage detection circuit; a first delay circuit which is connected to a drain of the first PMOS transistor; a second delay circuit which is connected to a drain of the second PMOS transistor; and a control circuit which is connected to an output terminal of the first delay circuit and an output terminal of the second delay circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification