Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
First Claim
1. A memory system comprising:
- an array of re-programmable non-volatile memory cells organized into distinct blocks of a plurality of simultaneously erasable memory cells, each block having a physical address and for storing units of data addressable by logical block addresses;
the logical block addresses being grouped into a plurality of distinct non-overlapping ranges of continuous logical block addresses;
a map of logical block addresses corresponding to physical addresses of the blocks; and
a controller for accessing at least one of the physical blocks in response to a logical block address received by the memory system by identifying at least one of the plurality of ranges in which the received logical block address exists and the physical address of the block being accessed that corresponds to the received logical block address within the identified range.
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Accused Products
Abstract
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.
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Citations
18 Claims
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1. A memory system comprising:
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an array of re-programmable non-volatile memory cells organized into distinct blocks of a plurality of simultaneously erasable memory cells, each block having a physical address and for storing units of data addressable by logical block addresses; the logical block addresses being grouped into a plurality of distinct non-overlapping ranges of continuous logical block addresses; a map of logical block addresses corresponding to physical addresses of the blocks; and a controller for accessing at least one of the physical blocks in response to a logical block address received by the memory system by identifying at least one of the plurality of ranges in which the received logical block address exists and the physical address of the block being accessed that corresponds to the received logical block address within the identified range. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification