Method and apparatus for using counter-mode encryption to protect image data in frame buffer of a video compression system

• US 8,503,671 B2
• Filed: 12/15/2011
• Issued: 08/06/2013
• Est. Priority Date: 04/05/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chen, Xuemin
• Primary Examiner(s): Cervetti, David Garcia
• Application Number:
  US13/326,984
• Publication Number:
  US 20120087498A1
• Time in Patent Office: 600 Days
• Field of Search: 380/210, 380/29, 380/217
• US Class Current: 380/29
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/2347 involving video stream encryption
• CPC Class Codes: H04N 21/4405 involving video stream decryption
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

Certain aspects for protecting image data in a video compression system may include encrypting image data utilizing counter-mode scrambling. The encrypted image data may be buffered in at least one frame buffer. The buffered encrypted image data may be decrypted by utilizing counter-mode descrambling.

Claims

1. A system for protecting image data in a video compression system, the system comprising:

one or more circuits for use in an encryption engine, said one or more circuits configured to;

encrypt image data utilizing counter-mode scrambling, said encrypting based on calculation of a row size of an encryption cipher; and

buffer said encrypted image data in at least one frame buffer.

2. The system according to claim 1, wherein said one or more circuits are configured to initialize a counter-mode scrambler counter to perform said counter-mode scrambling, wherein counter values for said counter mode scrambler counter utilized for said encrypting are pixel addressable.

3. The system according to claim 1, wherein said one or more circuits are configured to load an encryption key to perform said counter-mode scrambling.

4. The system according to claim 1, wherein said one or more circuits are configured to generate a ciphertext of said encrypted image data based on said calculated row size of said encryption cipher.

5. The system according to claim 1, wherein said one or more circuits are configured to store said encrypted image data along with its corresponding horizontal pixel address in an internal random access memory (RAM).

6. The system according to claim 1, wherein said one or more circuits are configured to arrange said buffered encrypted image data in raster scan order.

7. The system according to claim 1, wherein said one or more circuits are configured to generate said encrypted image data by exclusive-oring (XORing) at least one plaintext string M of said image data and a first |M| bits of a generated pad.

8. The system according to claim 7, wherein said one or more circuits are configured to pre-process said generated pad using spare processing cycles.

9. The system according to claim 1, wherein said encryption engine is configured to protect said buffered encrypted image data utilizing said counter-mode scrambling, wherein said buffered encrypted image data is compressed.

10. A method for protecting image data in a video compression system, the method comprising:

performing by one or more processors and/or circuits;

buffering encrypted image data in a frame buffer, wherein said image data is encrypted based on calculation of a row size of an encryption cipher.

11. A system for protecting image data in a video compression system, the system comprising:

one or more circuits for use in a decryption engine, said one or more circuits configured to;

buffer encrypted image data in one or more frame buffers; and

decrypt said buffered encrypted image data utilizing counter-mode descrambling, said decrypting based on calculation of a row size of a decryption cipher.

12. The system according to claim 11, wherein said one or more circuits are configured to initialize a counter-mode descrambler counter to perform said counter-mode descrambling, wherein counter values for said counter mode descrambler counter utilized for said decrypting are pixel addressable.

13. The system according to claim 11, wherein said one or more circuits are configured to load a decryption key to perform said counter-mode descrambling.

14. The system according to claim 11, wherein said one or more circuits are configured to decrypt a ciphertext of said encrypted image data based on said calculated row size of said decryption cipher.

15. The system according to claim 11, wherein said one or more circuits are configured to store said buffered encrypted image data along with its corresponding horizontal pixel address in an internal random access memory (RAM).

16. The system according to claim 11, wherein said one or more circuits are configured to arrange said buffered encrypted image data in raster scan order.

17. The system according to claim 11, wherein said one or more circuits are configured to generate said decrypted buffered encrypted image data by exclusive-oring (XORing) at least one ciphertext C of said buffered encrypted image data and a first |C| bits of a generated pad.

18. The system according to claim 17, wherein said one or more circuits are configured to pre-process said generated pad using spare processing cycles.

19. The system according to claim 11, wherein said one or more circuits are configured to protect said buffered encrypted image data utilizing said counter-mode descrambling, wherein said buffered encrypted image data is compressed.

20. The system according to claim 11, wherein said one or more circuits are configured to generate a pad E_K(ctr)∥

E_K(ctr+1)∥

E_K(ctr+2)∥

. . . ∥

E_K(ctr+m), where m is an integerof said decryption cipher utilizing said calculated row size, where E_K(X) denotes decipherment of an n-bit block X using a decryption key K and a block cipher E and ctr is a counter-mode descrambler counter.