Memory component having write operation with multiple time periods

• US 8,504,790 B2
• Filed: 03/19/2012
• Issued: 08/06/2013
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Davis, Paul G., Ware, Frederick A., Hampel, Craig E.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US13/424,273
• Publication Number:
  US 20120179866A1
• Time in Patent Office: 505 Days
• Field of Search: 711/105, 711/E12.008, 711/167, 711/169, 711/151, 711/152, 365/201, 365/230.01, 365/233.1
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

Claims

1. A method of operation of a memory controller chip that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the method comprising:

sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation;

after sending the write command, waiting for a first time period corresponding to a time period during which the write command is stored by the memory chip; and

sending data associated with the write operation to a second interface of the memory chip, wherein sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

2. The method of claim 1, further comprising:

sending to the first interface of the memory chip, a read command that specifies a read operation; and

after a read delay time, receiving, from the memory chip, read data corresponding to the read command.

3. The method of claim 2, wherein the first predetermined delay time corresponds to the read delay time minus a second predetermined delay time.

4. The method of claim 3, wherein the second predetermined delay time is a channel turnaround time.

5. A method of operation of a memory controller chip that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the method comprising:

sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation;

after sending the write command, waiting for a first time period corresponding to a time period during which the write command is stored by the memory chip;

sending data associated with the write operation to a second interface of the memory chip, wherein sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period; and

sending mask information that indicates to the memory chip whether to mask portions of the data to be written to the memory core of the memory chip during the write operation.

6. The method of claim 5, further comprising:

after sending the data, sending a retire command to the memory chip that indicates writing unmasked portions of the data to the memory core of the memory chip, wherein the unmasked portions of the data are bits of the data that are identified by the mask information as not being masked.

7. The method of claim 5, wherein the first predetermined delay time corresponds to a read delay time minus a second predetermined delay time.

8. The method of claim 7, further comprising:

sending to the memory chip a read command that specifies a read operation; and

after the read delay time, receiving from the memory chip read data corresponding to the read command.

9. The method of claim 7, wherein the second predetermined delay time is a channel turnaround time.

10. A controller apparatus that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the controller apparatus comprising an interface to send over an external interconnect:

a write command to a first interface of the memory chip, wherein the write command specifies a write operation; and

data associated with the write operation to a second interface of the memory chip, wherein the data is sent after a first predetermined delay time that includes both a first time period and a second time period, the first time period corresponding to a time period during which the write command is stored by the memory chip, and the second time period transpires following the first time period.

11. The controller apparatus of claim 10, wherein the interface of the controller apparatus is further to:

send over the external interconnect a read command to the first interface of the memory chip, wherein the read command specifies a read operation; and

receive from the memory chip, after a read delay time, read data corresponding to the read command.

12. The controller apparatus of claim 11, wherein the first predetermined delay time corresponds to the read delay time minus a second predetermined delay time.

13. The controller apparatus of claim 12, wherein the second predetermined delay time is a channel turnaround time.

14. A controller apparatus that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the controller apparatus comprising an interface to send over an external interconnect:

a write command to a first interface of the memory chip, wherein the write command specifies a write operation;

data associated with the write operation to a second interface of the memory chip, wherein the data is sent after a first predetermined delay time that includes both a first time period and a second time period, the first time period corresponding to a time period during which the write command is stored by the memory chip, and the second time period transpires following the first time period; and

mask information that indicates to the memory chip whether to mask portions of the data to be written to the memory core of the memory chip during the write operation.

15. The controller apparatus of claim 14, wherein the interface of the controller apparatus is further to send over the external interconnect, after sending the data, a retire command that indicates writing unmasked portions of the data in to the memory core of the memory chip, wherein the unmasked portions of the data are bits of the data that are identified by the mask information as not being masked.

16. The controller apparatus of claim 14, wherein the first predetermined delay time corresponds to a read delay time minus a second predetermined delay time.

17. The controller apparatus of claim 14, wherein the interface of the controller apparatus is further to:

send over the external interconnect a read command to first interface of the memory chip, wherein the read command specifies a read operation; and

receive from the memory chip, after a read delay time, read data corresponding to the read command.

18. The controller apparatus of claim 17, wherein the second predetermined delay time is a channel turnaround time.