Memory component having write operation with multiple time periods
First Claim
1. A method of operation of a memory controller chip that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the method comprising:
- sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation;
after sending the write command, waiting for a first time period corresponding to a time period during which the write command is stored by the memory chip; and
sending data associated with the write operation to a second interface of the memory chip, wherein sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.
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Abstract
A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.
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Citations
18 Claims
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1. A method of operation of a memory controller chip that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the method comprising:
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sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation; after sending the write command, waiting for a first time period corresponding to a time period during which the write command is stored by the memory chip; and sending data associated with the write operation to a second interface of the memory chip, wherein sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period. - View Dependent Claims (2, 3, 4)
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5. A method of operation of a memory controller chip that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the method comprising:
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sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation; after sending the write command, waiting for a first time period corresponding to a time period during which the write command is stored by the memory chip; sending data associated with the write operation to a second interface of the memory chip, wherein sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period; and sending mask information that indicates to the memory chip whether to mask portions of the data to be written to the memory core of the memory chip during the write operation. - View Dependent Claims (6, 7, 8, 9)
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10. A controller apparatus that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the controller apparatus comprising an interface to send over an external interconnect:
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a write command to a first interface of the memory chip, wherein the write command specifies a write operation; and data associated with the write operation to a second interface of the memory chip, wherein the data is sent after a first predetermined delay time that includes both a first time period and a second time period, the first time period corresponding to a time period during which the write command is stored by the memory chip, and the second time period transpires following the first time period. - View Dependent Claims (11, 12, 13)
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14. A controller apparatus that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells, the controller apparatus comprising an interface to send over an external interconnect:
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a write command to a first interface of the memory chip, wherein the write command specifies a write operation; data associated with the write operation to a second interface of the memory chip, wherein the data is sent after a first predetermined delay time that includes both a first time period and a second time period, the first time period corresponding to a time period during which the write command is stored by the memory chip, and the second time period transpires following the first time period; and mask information that indicates to the memory chip whether to mask portions of the data to be written to the memory core of the memory chip during the write operation. - View Dependent Claims (15, 16, 17, 18)
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Specification