Drift tracking feedback for communication channels

• US 8,504,863 B2
• Filed: 11/16/2009
• Issued: 08/06/2013
• Est. Priority Date: 03/17/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C, Chang, Kun-Yung, Lambrecht, Frank, Abhyankar, Abhijit M
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US12/619,076
• Publication Number:
  US 20100058100A1
• Time in Patent Office: 1,359 Days
• Field of Search: 713/400, 713/401, 713/500, 713/501, 713/503, 713/600
• US Class Current: 713/401
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0033 Correction by delay
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Claims

1. A memory controller comprising:

a first receiver to receive a read data signal from a DRAM, the first receiver having a sample timing signal;

a second receiver to receive a first signal from the DRAM, the first signal having a characteristic which drifts relative to the sample timing signal by amounts that correlate with drift in timing of the read data signal;

a monitoring circuit to monitor said characteristic of the first signal; and

an adjustment circuit to adjust reception of data by the first receiver based on said monitoring of the first signal by the monitoring circuit.

2. The controller of claim 1, the monitoring circuit to detect shifts in phase of the first signal;

and the adjustment circuit to adjust reception of data from the DRAM as a function of the shifts in phase.

3. The controller of claim 1, the adjustment circuit to adjust a sample timing point of a receiver on the DRAM.

4. The controller of claim 1, the adjustment circuit comprising logic to execute a calibration sequence to adjust a sample timing point of a receiver on the DRAM.

5. The controller of claim 1, the monitoring circuit comprising:

a phase detector to track changes in phase between the first signal and a reference signal; and

monitoring logic to issue an indication in response to the changes in phase, the adjustment circuit to adjust reception of data by the DRAM in response to the indication.

6. The controller of claim 5, the adjustment circuit to execute a calibration sequence in response to the indication.

7. The controller of claim 5, the monitoring logic to issue the indication when the phase of the first signal is shifted from the phase of the reference signal by a threshold amount.

8. The controller of claim 5, wherein the reference signal is a clock signal.

9. The controller of claim 1, the first signal comprising a timing reference signal generated by the DRAM.

10. The controller of claim 1, further comprising:

an interface to a bi-directional data link over which data is transmitted to the DRAM and data is received from the DRAM.

11. The controller of claim 10, wherein the bi-directional data link comprises a DQ link.

12. The controller of claim 11, wherein the first signal is unidirectional.

13. A memory controller comprising:

a first receiver to receive read data from a DRAM;

a second receiver to receive a first signal from the DRAM;

a transmitter to transmit a transmit data signal to the DRAM, the transmitter having a drive timing signal;

a monitoring circuit to detect transitions in the first signal, the first signal having transition times which drift relative to the drive timing signal by amounts that correlate with drift in timing of the transmit data signal; and

an adjustment circuit to adjust transmission of data by the transmitter to the DRAM as a function of the transitions in the first signal.

14. The controller of claim 13, further comprising a transmitter to transmit data to the DRAM, the adjustment circuit to adjust a drive timing point of the transmitter as a function of the transitions in the first signal.

15. The controller of claim 13, the adjustment circuit to adjust a sample timing point of a receiver on the DRAM.

16. The controller of claim 13, the adjustment circuit comprising logic to execute a calibration sequence.

17. The controller of claim 13, the monitoring circuit comprising:

a phase detector to track changes in phase between the first signal and a reference signal; and

monitoring logic to issue an indication in response to the changes in phase.

18. The controller of claim 17, the adjustment circuit to adjust the transmission of data to the DRAM in response to the indication.

19. The controller of claim 17, the adjustment circuit to execute a calibration sequence to adjust the transmission of data to the DRAM in response to the indication.

20. The controller of claim 17, the monitoring logic to issue the indication when the phase of the first signal is shifted from the phase of the reference signal by a threshold amount.

21. The controller of claim 13, the first signal comprising timing reference signal generated by the DRAM.

22. The controller of claim 13, further comprising:

an interface to a bi-directional data link over which data is transmitted to the DRAM and data is received from the DRAM.

23. The controller of claim 22, wherein the bi-directional data link comprises a DQ link.

24. The controller of claim 22, wherein the first signal is unidirectional.