Heat dissipation by through silicon plugs

• US 8,507,940 B2
• Filed: 09/10/2010
• Issued: 08/13/2013
• Est. Priority Date: 04/05/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Hung-Pin, Lin, Yung-Chi, Yu, Chia-Lin, Hung, Jui-Pin, Hwang, Chien Ling
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Page, Dale E
• Application Number:
  US12/879,584
• Publication Number:
  US 20110241061A1
• Time in Patent Office: 1,068 Days
• Field of Search: 257/99, 257/720, 257/717, 257/706, 257/675, 257/276, 257/E33.056
• US Class Current: 257/99
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32506 comprising an eutectic alloy
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/005 : Processes
• CPC Class Codes: H01L 33/0054 : for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/641 : characterized by the materials
• CPC Class Codes: H01L 33/644 : in intimate contact or integrated with parts of the device other than the semiconductor body
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

Claims

1. A semiconductor package substrate with through silicon plugs to dissipate heat generated by a packaged semiconductor chip, comprising:

a substrate with through silicon plugs (TSPs) on the semiconductor package substrate, wherein the TSPs extend from a first surface of the semiconductor package substrate to a second surface opposite to the first surface, wherein a cross-section of the TSPs show a pattern of double-sided combs, the double-sided combs including at least two TSPs contiguously connected by a thermally conductive material disposed within a material of the substrate, and wherein the TSPs provide heat dissipation pathways for the semiconductor chip.

2. The semiconductor package substrate of claim 1, wherein a duty ratio of the TSPs is equal to or greater than about 50%.

3. The semiconductor package substrate of claim 1, wherein a duty ratio of the TSPs is equal to or less than about 65%.

4. The semiconductor package substrate of claim 1, wherein a duty ratio of the TSPs is equal to or greater than about 30%.

5. The semiconductor package substrate of claim 1, a width of the pattern of double-sided combs of TSPs is between about 5 μ

m to about 100 μ

m.

6. The semiconductor package substrate of claim 1, a space between TSPs of the pattern of double-sided combs of TSPs is between about 5 μ

m to about 100 μ

m, and wherein the space is equal to or greater than a width of the pattern of double-sided combs.

7. The semiconductor package substrate of claim 1, wherein the semiconductor chip is a light-emitting diode (LED) chip.

8. The semiconductor package substrate of claim 1, wherein each of the double-sided combs comprises two or more sub-structures of double-sided combs.

9. The semiconductor package substrate of claim 8, wherein each of the double-sided combs has a length of between about 100 μ

m to about 300 μ

m.

10. The semiconductor package substrate of claim 1, wherein each of the double-sided combs has a width of between about 100 μ

m to about 300 μ

m.

11. The semiconductor package substrate of claim 7, wherein an area of the cross-section of the TSPs is larger than a surface area of the LED chip facing the semiconductor package substrate.

12. The semiconductor package substrate of claim 10, wherein there is a metal layer between the LED chip and the TSPs, and wherein the metal layer provides lateral heat dissipation pathways for the LED chip.

13. The semiconductor package substrate of claim 1, wherein the TSPs are filled with copper.

14. The semiconductor package substrate of claim 7, wherein the TSPs are part of a P-contact for the LED chip, and wherein the semiconductor package substrate contains additional TSPs, where the additional TSPs are part of an N-contact for the LED chip.

15. The semiconductor package substrate of claim 8, wherein the pattern of double-sided combs are formed by a number of sub-structures of doubled-side combs, and wherein the number is selected from a group consisting of 4, 16, 49, 12, or 81.

16. The semiconductor package substrate of claim 1, wherein two neighboring double-sided combs of the pattern of double-sided combs are placed in a staggered pattern.

17. A semiconductor package substrate with through silicon plugs to dissipate heat generated by a semiconductor chip being packaged, comprising:

a substrate with through silicon plugs (TSPs) on the semiconductor package substrate, wherein the TSPs extend from a first surface of the semiconductor package substrate to a second surface opposite to the first surface, wherein the TSPs have a duty ratio equal to or greater than about 50%, and a cross-section of the TSPs show a pattern of double-sided combs, the double-sided combs including at least two TSPs contiguously connected by a thermally conductive material disposed within a material of the substrate.

18. The semiconductor package substrate of claim 17, wherein a width of the pattern of double-sided combs of TSPs is between about 5 μ

m to about 100 μ

m, and wherein a space between combs of the pattern of double-sided combs of TSPs is between about 5 μ

m to about 100 μ

m.

19. The semiconductor package substrate of claim 17, wherein the semiconductor chip is a light-emitting diode (LED) chip.

20. The semiconductor package substrate of claim 17, further comprising a plurality of TSPs, wherein two neighboring double-sided combs of the pattern of double-sided combs are staggered in a direction perpendicular to the first surface.