Semiconductor device including an insulated gate bipolar transistor (IGBT)

• US 8,507,945 B2
• Filed: 03/31/2008
• Issued: 08/13/2013
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Nakamura, Katsumi
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US12/867,832
• Publication Number:
  US 20100327313A1
• Time in Patent Office: 1,961 Days
• Field of Search: 257/330, 257146-147
• US Class Current: 257/146
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes a semiconductor substrate and a MOS transistor. The semiconductor substrate has the first main surface and the second main surface facing each other. The MOS transistor includes a gate electrode (5a) formed on the first main surface side, an emitter electrode (11) formed on the first main surface side, and a collector electrode (12) formed in contact with the second main surface. An element generates an electric field in a channel by a voltage applied to the gate electrode (5a), and controls the current between the emitter electrode (11) and the collector electrode (12) by the electric field in the channel. The spike density in the interface between the semiconductor substrate and the collector electrode (12) is not less than 0 and not more than 3×10⁸ unit/cm². Consequently, a semiconductor device suitable for parallel operation is provided.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

an impurity concentration of said collector diffusion layer in an interface between said second electrode and said collector diffusion layer is not less than 5.0×

10¹⁵ cm<sup>−

3</sup> and not more than 1.0×

10²² cm<sup>−

3</sup>.

2. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

a maximum value of an impurity concentration of said collector diffusion layer is not less than 1.0×

10¹⁶ cm<sup>−

3</sup> and not more than 1.0×

10²² cm<sup>−

3</sup>.

3. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

a depth from said second main surface to a junction plane between said collector diffusion layer and said buffer diffusion layer is greater than 0 and not more than 1.0 μ

m.

4. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

said collector region further includes a drift diffusion layer of the second conductivity type, and said drift diffusion layer is lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer and closer to the first main surface than said buffer diffusion layer is, and

a depth from said second main surface to a junction plane between said buffer diffusion layer and said drift diffusion layer is not less than 0.4 μ

m and not more than 50 μ

m.

5. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

a carrier lifetime in said buffer diffusion layer is less than a carrier lifetime in said collector diffusion layer.

6. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

said collector region further includes a drift diffusion layer of the second conductivity type, and said drift diffusion layer is lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer and closer to the first main surface than said buffer diffusion layer is, and

a carrier lifetime in a range of a depth of not less than 0.50 μ

m and not more than 60.0 μ

m from said second main surface is less than a carrier lifetime in said drift diffusion layer.

7. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

said collector diffusion layer is lower in activation rate than said buffer diffusion layer.

8. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

an activation rate in said collector diffusion layer is greater than 0 and not more than 90%.

9. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

a depth from said second main surface to a position where an impurity concentration of said buffer diffusion layer reaches a maximum value is not less than 0.40 μ

m and not more than 50 μ

m.

10. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

a ratio of a maximum value of an impurity concentration in said collector diffusion layer to a maximum value of an impurity concentration in said buffer diffusion layer is not less than 1.0 and not more than 1.0×

10³.

11. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

said collector region further includes a drift diffusion layer of the second conductivity type, and said drift diffusion layer is lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer and closer to the first main surface than said buffer diffusion layer is, and

a ratio of the number of atoms per unit area of impurities forming said buffer diffusion layer to the number of atoms per unit area of impurities forming said drift diffusion layer is not less than 0.05 and not more than 100.

12. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, and a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, wherein

said collector region further includes an intermediate layer of the second conductivity type, and said intermediate layer is lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer, and

a ratio of the number of atoms per unit area of impurities forming said intermediate layer to the number of atoms per unit area of impurities forming said buffer diffusion layer is greater than 0 and not more than 0.50.

13. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface, and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a collector region formed on said second main surface, said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, a buffer diffusion layer of a second conductivity type formed closer to said first main surface than said collector diffusion layer is, and a drift diffusion layer of the second conductivity type, and said drift diffusion layer being lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer and closer to the first main surface than said buffer diffusion layer is, wherein

a ratio of the number of atoms per unit area of impurities forming said buffer diffusion layer to the number of atoms per unit area of impurities forming said drift diffusion layer is not less than 0.05 and not more than 100.

14. The semiconductor device according to claim 13, wherein an impurity concentration of said collector diffusion layer in an interface between said second electrode and said collector diffusion layer is not less than 5.0×

10¹⁵ cm<sup>−

3</sup> and not more than 1.0×

10²¹ cm<sup>−

3</sup>.

15. The semiconductor device according to claim 13, wherein a maximum value of the impurity concentration of said collector diffusion layer is not less than 1.0×

10¹⁶ cm<sup>−

3</sup> and not more than 1.0×

10²¹ cm<sup>−

3</sup>.

16. The semiconductor device according to claim 13, wherein a depth from said second main surface to a junction plane between said collector diffusion layer and said buffer diffusion layer is greater than 0 and not more than 1.0 μ

m.

17. The semiconductor device according to claim 13, wherein a depth from said second main surface to a junction plane between said buffer diffusion layer and said drift diffusion layer is not less than 0.4 μ

m and not more than 50 μ

m.

18. The semiconductor device according to claim 13, wherein a carrier lifetime in said buffer diffusion layer is less than a carrier lifetime in said collector diffusion layer.

19. The semiconductor device according to claim 13, wherein a carrier lifetime in a range of a depth of not less than 0.50 μ

m and not more than 60.0 μ

m from said second main surface is less than a carrier lifetime in said drift diffusion layer.

20. The semiconductor device according to claim 13, wherein said collector diffusion layer is lower in activation rate than said buffer diffusion layer.

21. The semiconductor device according to claim 13, wherein an activation rate in said collector diffusion layer is greater than 0 and not more than 90%.

22. The semiconductor device according to claim 13, wherein a depth from said second main surface to a position where the impurity concentration of said buffer diffusion layer reaches a maximum value is not less than 0.40 μ

m and not more than 50 μ

m.

23. The semiconductor device according to claim 13, wherein a ratio of a maximum value of the impurity concentration in said collector diffusion layer to a maximum value of the impurity concentration in said buffer diffusion layer is not less than 1.0 and not more than 1.0×

10³.

24. The semiconductor device according to claim 13, wherein the ratio of the number of atoms per unit area of impurities forming said buffer diffusion layer to the number of atoms per unit area of impurities forming said drift diffusion layer is not less than 0.05 and not more than 100.

25. The semiconductor device according to claim 13, wherein said second main surface has a center line average roughness of greater than 0 and not more than 200 nm.

26. The semiconductor device according to claim 13, wherein a maximum height of said second main surface is greater than 0 and not more than 2000 nm.

27. The semiconductor device according to claim 13, wherein a gate groove is formed in said first main surface of said semiconductor substrate, and said gate groove is filled with said gate electrode.

28. The semiconductor device according to claim 27, wherein

a plurality of grooves are formed in said first main surface of said semiconductor substrate and said gate groove is at least one of said plurality of grooves, and

a ratio of a depth from said first main surface to a bottom of said gate groove to a pitch between said gate groove and another groove adjacent thereto is not less than 1.0.

29. The semiconductor device according to claim 27, wherein a plurality of grooves are formed in said first main surface of said semiconductor substrate, said plurality of grooves are arranged in one direction as seen in plan view, and said gate groove is at least one of said plurality of grooves, said semiconductor device further comprises a well layer of the first conductivity type formed on said first main surface adjacent to each of said plurality of grooves, extending in said one direction as seen in plan view, and formed deeper than each of said plurality of grooves, and

a depth from a bottom surface of said gate groove to a bottom of said well layer is greater than 0 and not more than 1.0 μ

tm.

30. The semiconductor device according to claim 13, further comprising:

a body diffusion layer of the first conductivity type serving as said channel; and

a buried diffusion layer of the second conductivity type formed between said body diffusion layer and said drift diffusion layer.

31. The semiconductor device according to claim 30, wherein a groove is formed in said first main surface of said semiconductor substrate, and said groove protrudes toward the second main surface with respect to a position where the impurity concentration in said buried diffusion layer reaches 1 ×

10¹⁶ cm<sup>−

3</sup>.

32. The semiconductor device according to claim 30, wherein

a gate groove and an emitter groove are formed in said first main surface of said semiconductor substrate, said gate groove is filled with said gate electrode, and said emitter groove is filled with a conductive layer having said emitter potential, and

said buried diffusion layer is formed so as to be brought into contact with an emitter groove but not with the gate groove.

33. The semiconductor device according to claim 32, wherein said buried diffusion layer has a width of not less than 6.0 μ

m and not more than 9 μ

m as seen in plan view in a region existing around said emitter groove.

34. The semiconductor device according to claim 32, wherein a distance from said emitter groove to an end of said buried diffusion layer is not less than 0.5 μ

m and not more than 2 μ

m.

35. The semiconductor device according to claim 30, wherein

a gate groove and an emitter groove are formed in said first main surface of said semiconductor substrate, said gate groove is filled with said gate electrode, and said emitter groove is filled with a conductive layer having an emitter potential, and

said buried diffusion layer is formed so as to be brought into contact with said gate groove but not with the emitter groove.

36. The semiconductor device according to claim 30, wherein

a plurality of grooves are formed in said first main surface of said semiconductor substrate, and said plurality of grooves are arranged in one direction as seen in plan view, and

said buried diffusion layer is formed only in a region interposed between said grooves as seen in plan view.

37. The semiconductor device according to claim 36, further comprising a well layer of the first conductivity type formed on said first main surface adjacent to said plurality of grooves in a direction in which said plurality of grooves are arranged, extending in said one direction as seen in plan view and formed deeper than each of said plurality of grooves, wherein

said well layer is formed deeper than said buried diffusion layer.

38. The semiconductor device according to claim 13, further comprising:

a first emitter diffusion layer of the first conductivity type formed on said first main surface and in contact with said first electrode; and

a second emitter diffusion layer of the second conductivity type formed on said first main surface and in contact with said first electrode and said first emitter diffusion layer, wherein

a ratio of a width of said first second emitter diffusion layer along a direction in which said gate electrode extends to a sum of said width of the first emitter diffusion layer and a width of the second emitter diffusion layer along the direction in which said gate electrode extends is not less than 0.08 and not more than 0.20.

39. The semiconductor device according to claim 13, wherein an electric signal is transmitted to said gate electrode through a resistor body having a locally high electrical resistance value.

40. The semiconductor device according to claim 39, wherein said resistor body is identical in structure to said gate electrode.

41. The semiconductor device according to claim 13, further comprising a body diffusion layer of the first conductivity type being in contact with said collector region and serving as said channel, wherein

an electric field intensity in a junction plane between said drift diffusion layer and said body diffusion layer obtained when a reverse voltage is applied to said element is greater than 0 and not more than 3.0 ×

10⁵ V/cm.

42. The semiconductor device according to claim 13, further comprising a body diffusion layer of the first conductivity type being in contact with said collector region and serving as said channel, wherein

an electric field intensity in a junction plane between said buffer diffusion layer and said drift diffusion layer obtained when a reverse voltage is applied to said element is not less than 2.0 ×

10⁴ V/cm and not more than an electric field intensity in a junction plane between said drift diffusion layer and said body diffusion layer.

43. The semiconductor device according to claim 13, further comprising a body diffusion layer of the first conductivity type serving as said channel, wherein

a gate groove is formed in said first main surface of said semiconductor substrate, and said gate groove is filled with said gate electrode, and

a protrusion amount of said gate groove from a bottom of said body diffusion layer is not less than 1.0 μ

m and not more than a depth reaching said second main surface.

44. The semiconductor device according to claim 13, further comprising:

a body diffusion layer of the first conductivity type serving as said channel; and

a buried diffusion layer of the second conductivity type formed adjacent to a side surface of said body diffusion layer as seen in plan view.

45. The semiconductor device according to claim 44, wherein a ratio of the number of atoms per unit area of impurities forming said buried diffusion layer the number of atoms per unit area of impurities forming said drift diffusion layer is not less than 0 and not more than 20.