Semiconductor device and manufacturing method of the same

• US 8,507,977 B2
• Filed: 06/29/2012
• Issued: 08/13/2013
• Est. Priority Date: 01/28/2009
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sasaki, Yuji
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US13/538,688
• Publication Number:
  US 20120267707A1
• Time in Patent Office: 410 Days
• Field of Search: 438/268, 257/E21.41, 257/329, 257/339, 257/E29.262
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.

Claims

1. A semiconductor device, comprising:

a semiconductor body;

a plurality of first semiconductor regions in the first semiconductor body;

a plurality of second semiconductor regions located between adjacent ones of the first semiconductor regions;

the first and second semiconductor regions having both element and termination regions,

transistors are formed in the element region of the first and second semiconductor regions, and wherein there are no transistors formed in the termination region of the first and second semiconductor regions;

each transistor in the element region has portions formed at a surface of a corresponding first semiconductor region and in contact with a corresponding second semiconductor region; and

wherein a void is formed in at least some of the second regions in the termination region.

2. The semiconductor device of claim 1, wherein

a gate insulating film is formed over each first semiconductor region in the element region;

a gate electrode formed on the gate insulating film in such a manner as to cover part of the surface of the first semiconductor region;

a source region formed at end portions of the gate electrode.

3. The semiconductor device of claim 1, wherein

each of a plurality of the second semiconductor regions in the termination region are shaped differently from a corresponding second semiconductor region in the element region.

4. The semiconductor device of claim 3, wherein

the second semiconductor region in the termination region is formed so as to gradually increase in thickness extending from the element region.

5. The semiconductor device of claim 3, wherein

the first semiconductor region in the termination region is formed so as to gradually decrease in thickness from the element region.

6. The semiconductor device of claim 3, wherein

the end portions of the second semiconductor region in the termination region are formed with a trapezoidal shape and wider than a corresponding second semiconductor region in the element region.