Electronic devices

• US 8,508,034 B2
• Filed: 01/31/2012
• Issued: 08/13/2013
• Est. Priority Date: 09/16/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bolken, Todd O., Baerlocher, Cary J., Heppler, Steven W., Cobbley, Chad A.
• Primary Examiner(s): Coleman, William D
• Application Number:
  US13/362,644
• Publication Number:
  US 20120126386A1
• Time in Patent Office: 560 Days
• Field of Search: 257/692, 257/E23.067, 257/680, 257/E33.066
• US Class Current: 257/692
• CPC Class Codes: B33Y 80/00 Products made by additive manufacturing
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48997 Reinforcing structures
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/28 : Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49861 : Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover.

Claims

1. An electronic device, comprising:

a package structure having a top surface and an opposing, bottom surface, a cavity in the package structure including a die mounting surface and an upwardly extending sidewall from the die mounting surface to the top surface of the package structure, the sidewall having at least a portion thereof oriented at an outward angle relative to the die mounting surface of greater than 90°

;

a semiconductor die located at the die mounting surface;

an optically transparent lens located within the cavity and insulated from direct contact with the semiconductor die;

at least one contact pad adjacent the die mounting surface located for electrical connection to the semiconductor die;

at least one attachment pad on the bottom surface; and

at least one conductive element passing through the package structure and electrically connecting the at least one contact pad and the at least one attachment pad.

2. The electronic device of claim 1, wherein the package structure comprises a dielectric.

3. The electronic device of claim 1, wherein the semiconductor die includes at least one bond pad, electrically connected to the at least one contact pad.

4. The electronic device of claim 3, wherein the at least one bond pad is electrically connected to the at least one contact pad by a connection selected from the group consisting of bond wires, solder, conductive epoxy, and conductor-filled epoxy.

5. The electronic device of claim 3, wherein the at least one bond pad is electrically connected to the at least one contact pad by a flip-chip connection.

6. A semiconductor device, comprising:

a package structure having a die mounting area over a surface thereof within a cavity, the package structure further including a sidewall of the cavity extending above the surface and facing the die mounting area, at least a portion of the sidewall inclined at an outward angle of greater than about 90°

relative to the surface;

at least one contact pad exposed on an interior surface of the cavity;

a semiconductor die in the die mounting area electrically connected to the at least one contact pad;

at least one attachment pad exposed on a surface of the package structure other than the surface;

at least one conductive structure passing through the package structure and electrically connecting the at least one contact pad and the at least one attachment pad; and

an optically transparent lens within the cavity isolated from direct contact with the semiconductor die.

7. The semiconductor device of claim 6, wherein the package structure comprises a dielectric material.

8. The semiconductor device of claim 6, wherein the semiconductor die includes a plurality of bond pads, the at least one contact pad comprises a plurality of contact pads, and at least some of the bond pads of the plurality are electrically connected to contact pads of the plurality.

9. The semiconductor device of claim 8, wherein the at least some of the bond pads of the plurality are electrically connected to contact pads of the plurality by connections selected from the group consisting of bond wires, solder, conductive epoxy, or conductor-filled epoxy.

10. The semiconductor device of claim 8, wherein the at least some of the bond pads of the plurality are electrically connected to contact pads of the plurality by flip-chip connections.

11. A packaged semiconductor chip, comprising:

a substrate structure having a first surface, an opposing, second surface, and a raised sidewall protruding above the first surface, extending along a perimeter of the substrate structure and defining a chip cavity, the raised sidewall comprising an upwardly facing, inclined surface surrounding the chip cavity;

a semiconductor chip over the first surface within the chip cavity;

a transparent lens element within the chip cavity, the transparent lens element insulated from contact with the semiconductor chip;

at least one contact pad exposed adjacent the first surface and electrically connected to the semiconductor chip;

at least one attachment pad exposed adjacent the second surface; and

at least one conductive path electrically connecting the at least one contact pad to the at least one attachment pad through the substrate structure.

12. The packaged semiconductor chip of claim 11, wherein the substrate structure comprises a dielectric material at least adjacent to the at least one conductive path.

13. The packaged semiconductor chip of claim 11, wherein the semiconductor chip is electrically connected to the at least one contact pad by a flip-chip connection.

14. The packaged semiconductor chip of claim 11, wherein the semiconductor chip is electrically connected to the at least one contact pad by a connection selected from the group consisting of bond wires, solder, conductive epoxy, and conductor-filled epoxy.

15. The packaged semiconductor chip of claim 11, further comprising a material disposed over at least a portion of the upwardly facing, inclined surface.

16. A packaged electronic device, comprising:

a structure having a first surface and including a sidewall surrounding the first surface to form a die cavity, the sidewall having at least a portion thereof oriented at an outward angle relative to the first surface of greater than about 90°

;

at least one contact pad adjacent the first surface;

a semiconductor die located above the first surface within the die cavity and electrically connected to the at least one contact pad;

an optically clear lens within the chip die extending over the semiconductor die and isolated from direct contact with the semiconductor die;

at least one attachment pad adjacent another surface of the structure; and

at least one conductor passing through the structure and electrically connecting the at least one contact pad and the at least one attachment pad.

17. The packaged electronic device of claim 16, wherein the structure comprises a dielectric material.

18. A chip package, comprising:

a substrate structure having a chip mounting surface, an opposing surface, and a raised sidewall protruding above the chip mounting surface, extending along a perimeter of the substrate structure and bounding a chip cavity, the raised sidewall comprising an upwardly facing, inclined surface adjacent to the chip cavity;

at least one contact pad exposed adjacent the chip mounting surface;

a semiconductor chip disposed in the chip cavity and electrically connected to the at least one contact pad;

a transparent cover having a optical focusing structure extending over the semiconductor chip within the chip cavity and out of contact with the semiconductor chip;

at least one attachment pad exposed adjacent the opposing surface; and

at least one conductive path electrically connecting the at least one contact pad to the at least one attachment pad through the substrate structure.

19. The chip package of claim 18, wherein the substrate structure comprises a dielectric.

20. The chip package of claim 18, wherein the semiconductor chip is electrically connected to the at least one contact pad by an intermediate conductive element.