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Wafer scale chip scale packaging of vertically integrated MEMS sensors with electronics

  • US 8,508,039 B1
  • Filed: 05/08/2008
  • Issued: 08/13/2013
  • Est. Priority Date: 05/08/2008
  • Status: Active Grant
First Claim
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1. A MEMS package comprising:

  • a MEMS die containing;

    a first substrate comprising a substrate with a CMOS device, wherein the CMOS device includes a plurality of CMOS pads;

    a second substrate comprising a MEMS subassembly, bonded to the first substrate;

    a third substrate comprising a cover and bonded to the MEMS subassembly;

    the MEMS subassembly having generally a planar surface and an edge surfaces;

    a fourth substrate adhesively attached on top of a planar surface of the third substrate; and

    wherein the MEMS subassembly is highly doped silicon and electrically insulated from the third substrate;

    wherein there are silicon islands formed out of the second substrate, wherein the silicon islands are electrically isolated from the rest of the second substrate, wherein silicon islands are attached to the third substrate;

    wherein the silicon islands have stand offs with conducting layers;

    wherein the stand offs with conductive layers can form an electrical connection to the plurality of CMOS pads on the CMOS device of the first substrate;

    wherein solder balls are formed on a top side of the fourth substrate and are electrically connected to the plurality of CMOS pads, a layer of insulation between the third and fourth substrates;

    wherein a metallization attached on the edge surface of the fourth substrates and on top of the layer of insulation covering the edge of the third substrate, wherein the metallization is attached on the edge surface of the second substrate to the plurality of silicon islands, wherein the plurality of silicon islands are without insulation and one of the silicon islands makes an ohmic electrical connections to the metallization, wherein the plurality of silicon islands provide the final connection to the plurality of CMOS pads on the CMOS device.

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