Bonding method for three-dimensional integrated circuit and three-dimensional integrated circuit thereof

• US 8,508,041 B2
• Filed: 12/14/2011
• Issued: 08/13/2013
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: National Chiao Tung University (Government of The Republic of China)
• Inventors: Chen, Kuan-Neng, Hsu, Sheng-Yao
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/325,587
• Publication Number:
  US 20130069248A1
• Time in Patent Office: 608 Days
• Field of Search: 257/431, 257/678, 257/687, 257/713, 257/717, 257/720, 257/781, 257/782, 257/783, 257/E21.006, 257/E21.077, 257/E21.081, 257/E21.084, 257/E21.088, 257/E21.267, 257/E21.311, 257/E21.321
• US Class Current: 257/713
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/16137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16501 at the bonding interface
• CPC Class Codes: H01L 2224/16505 outside the bonding interface, e.g. in the bulk of the bump connector
• CPC Class Codes: H01L 2224/81055 being oxidating
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8183 Solid-solid interdiffusion
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/05341 : TiO2

Abstract

The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit.

Claims

1. A three-dimensional integrated circuit, comprising:

a first integrated circuit, comprising;

a first substrate;

a first film layer, formed on the first substrate, having a first pattern structure formed thereon; and

a first metal co-deposition layer disposed on the first film layer, having a first metal and a second metal deposited therewithin; and

a second integrated circuit, comprising;

a second substrate;

a second film layer, formed on the second substrate, having a second pattern structure formed thereon; and

a second metal co-deposition layer disposed on the second film layer, having the first metal and the second metal deposited therewithin;

wherein the second integrated circuit is superimposed onto the first integrated circuit at a predetermined temperature, such that the first metal co-deposition layer and the second metal co-deposition layer are bonded with each other, and at least a portion of atoms of the first metal diffuse toward a bonding interface between the first metal co-deposition layer and the second metal co-deposition layer, and at least a portion of atoms of the second metal diffuse toward the respective film layers of each of the integrated circuits to form adhesion and barrier layers for the first metal.

2. The three-dimensional integrated circuit of claim 1, wherein the adhesion and barrier layers provides a more stable adhesiveness between the first metal and the film layers, and inhibits the atoms of the first metal from diffusing into the film layers.

3. The three-dimensional integrated circuit of claim 1, wherein the predetermined temperature is between 200°

C. and 400°

C.

4. The three-dimensional integrated circuit of claim 1, wherein the superimposing step is carried out under atmospheric ambient environment.

5. The three-dimensional integrated circuit of claim 1, wherein at least another portion of the atoms of the second metal at peripheries of the co-deposition layers react with oxygen, and thereby forming a boundary protection layer to protect the first metal from oxidization.

6. The three-dimensional integrated circuit of claim 5, wherein the first metal is copper and the second metal is titanium.

7. A three-dimensional integrated circuit, comprising:

a first integrated circuit, having a first substrate, a first film layer and a first metal co-deposition layer sequentially; and

a second integrated circuit, having a second metal co-deposition layer, a second film layer and a second substrate sequentially;

wherein, the first metal co-deposition layer and the second metal co-deposition layer are bonded with each other at a predetermined temperature, and an adhesion and barrier layer is formed near the first film layer or the second film layer, and a boundary protection layer is formed near a surface of the first metal co-deposition layer or the second metal co-deposition layer.

8. The three-dimensional integrated circuit of claim 7, wherein the first metal co-deposition layer and the second metal co-deposition layer are bonded with each other at the predetermined temperature and under atmospheric ambient environment.

9. The three-dimensional integrated circuit of claim 7, wherein the first metal co-deposition layer and the second metal co-deposition layer are bonded with each other in a cavity at the predetermined temperature.