Semiconductor integrated circuit

• US 8,508,256 B2
• Filed: 05/15/2012
• Issued: 08/13/2013
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yakubo, Yuto, Nagatsuka, Shuhei
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US13/471,922
• Publication Number:
  US 20120293210A1
• Time in Patent Office: 455 Days
• Field of Search: 326/102, 326/83, 326/52, 326/55, 326/95, 326/112, 326/113, 326/122, 327/408, 327/409
• US Class Current: 326/103
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.

Claims

1. A logic circuit including:

a first transistor whose gate is electrically connected to one of a source or a drain of a second transistor;

a third transistor whose gate is electrically connected to one of a source or a drain of a fourth transistor;

a fifth transistor whose gate is electrically connected to one of a source or a drain of a sixth transistor;

a seventh transistor whose gate is electrically connected to one of a source or a drain of an eighth transistor;

a ninth transistor whose gate is electrically connected to one of a source or a drain of a tenth transistor;

an eleventh transistor whose gate is electrically connected to one of a source or a drain of a twelfth transistor;

a thirteenth transistor whose gate is electrically connected to one of a source or a drain of a fourteenth transistor; and

a fifteenth transistor whose gate is electrically connected to one of a source or a drain of a sixteenth transistor including an oxide semiconductor; and

a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a twenty-first transistor,

wherein each of the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, the eleventh transistor, the thirteenth transistor and the fifteenth transistor includes silicon,

wherein each of the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, the tenth transistor, the twelfth transistor, the fourteenth transistor and the sixteenth transistor includes an oxide semiconductor,

wherein one of a source and a drain of the eighteenth transistor, one of a source and a drain of the nineteenth transistor, one of a source and a drain of the twentieth transistor and one of a source and a drain of the twenty-first transistor are electrically connected to each other,

wherein the other of the source and the drain of the eighteenth transistor, a gate of the twentieth transistor, one of a source and a drain of the first transistor, and one of a source and a drain of the fifth transistor are electrically connected to each other at a first node,

wherein the other of the source and the drain of the twenty-first transistor, a gate of the nineteenth transistor, one of a source and a drain of the ninth transistor, and one of a source and a drain of the thirteenth transistor are electrically connected to each other at a second node,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to one of a source and a drain of the eleventh transistor,

wherein the other of the source and the drain of the thirteenth transistor is electrically connected to one of a source and a drain of the fifteenth transistor, and

wherein the other of the source and the drain of the third transistor, the other of the source and the drain of the seventh transistor, the other of the source and the drain of the eleventh transistor, the other of the source and the drain of the fifteenth transistor and one of a source and a drain of the seventeenth transistor are electrically connected to each other.

2. The logic circuit according to claim 1, further comprising:

a comparator including the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor; and

an output-node-potential determining portion comprising the seventeenth transistor,

wherein each of the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor is a p-channel transistor,

wherein the seventeenth transistor is an n-channel transistor,

and

wherein each of a gate of the eighteenth transistor, a gate of the twenty-first transistor and a gate of the seventeenth transistor is supplied with a clock signal.

3. The logic circuit according to claim 1, further comprising:

a comparator including the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor; and

an output-node-potential determining portion comprising the seventeenth transistor,

wherein each of the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor is an n-channel transistor,

wherein the seventeenth transistor is a p-channel transistor, and

wherein each of a gate of the eighteenth transistor, a gate of the twenty-first transistor and a gate of the seventeenth transistor is supplied with a clock signal.

4. The logic circuit according to claim 1, wherein the logic circuit is an XOR circuit.

5. The logic circuit according to claim 1, wherein the logic circuit is a MUX circuit.

6. A semiconductor integrated circuit comprising the logic circuit according to claim 1.

7. A logic circuit comprising:

a first node and a second node;

a comparator configured to compare potentials of the first and the second node;

a charge retaining portion electrically connected to the comparator via the first node and the second node; and

an output-node-potential determining portion electrically connected to the charge retaining portion,

wherein the charge retaining portion comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes an oxide semiconductor,

wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the first transistor,

wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a gate of the eighth transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the thirteenth transistor is electrically connected to one of a source and a drain of the ninth transistor,

wherein a gate of the fourteenth transistor is electrically connected to one of a source and a drain of the tenth transistor,

wherein a gate of the fifteenth transistor is electrically connected to one of a source and a drain of the eleventh transistor,

wherein a gate of the sixteenth transistor is electrically connected to one of a source and a drain of the twelfth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first node,

wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the first node,

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor,

wherein one of a source and a drain of the thirteenth transistor is electrically connected to the second node,

wherein one of a source and a drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor,

wherein one of a source and a drain of the fifteenth transistor is electrically connected to the second node,

wherein one of a source and a drain of the sixteenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor, and

wherein the output-node-potential determining portion comprises a seventeenth transistor whose source or drain is electrically connected to the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source or the drain of the fourteenth transistor and the other of the source or the drain of the sixteenth transistor.

8. The logic circuit according to claim 7, wherein each of the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the seventeenth transistor includes silicon.

9. The logic circuit according to claim 7,

wherein the seventeenth transistor is an n-channel transistor,

wherein the comparator includes a first p-channel transistor, a second p-channel transistor, a third p-channel transistor and a fourth p-channel transistor,

wherein a source or a drain of the first p-channel transistor and a source or a drain of the second p-channel transistor are electrically connected to the first node,

wherein a source or a drain of the third p-channel transistor and a source or a drain of the fourth p-channel transistor are electrically connected to the second node,

wherein a gate of the second p-channel transistor is electrically connected to the second node,

wherein a gate of the third p-channel transistor is electrically connected to the first node, and

wherein a gate of the first p-channel transistor, a gate of the fourth p-channel transistor and a gate of the seventeenth transistor are supplied with a clock signal.

10. The logic circuit according to claim 7,

wherein the seventeenth transistor is a p-channel transistor,

wherein the comparator includes a first n-channel transistor, a second n-channel transistor, a third n-channel transistor and a fourth n-channel transistor,

wherein a source or a drain of the first n-channel transistor and a source or a drain of the second n-channel transistor are electrically connected to the first node,

wherein a source or a drain of the third n-channel transistor and a source or a drain of the fourth n-channel transistor are electrically connected to the second node,

wherein a gate of the second n-channel transistor is electrically connected to the second node,

wherein a gate of the third n-channel transistor is electrically connected to the first node, and

wherein a gate of the first n-channel transistor, a gate of the fourth n-channel transistor and a gate of the seventeenth transistor are supplied with a clock signal.

11. The logic circuit according to claim 9,

each of a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, a gate of the fourth transistor, a gate the ninth transistor, a gate of the tenth transistor, a gate of the eleventh transistor and a gate of the twelfth transistor is supplied with an inverted signal of the clock signal,

wherein each of the other of the source and the drain of the first transistor and the other of the source and the drain of the eleventh transistor is supplied with a first input signal,

wherein each of the other of the source and the drain of the third transistor and the other of the source and the drain of the ninth transistor is supplied with an inverted signal of the first input signal,

wherein each of the other of the source and the drain of the fourth transistor and the other of the source and the drain of the twelfth transistor is supplied with a second input signal, and

wherein each of the other of the source and the drain of the second transistor and the other of the source and the drain of the tenth transistor is supplied with an inverted signal of the second input signal.

12. The logic circuit according to claim 9,

wherein each of a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, a gate of the fourth transistor, a gate of the ninth transistor, a gate of the tenth transistor, a gate of the eleventh transistor and a gate of the twelfth transistor is supplied with an inverted signal of the clock signal,

wherein the other of the source and the drain of the first transistor is supplied with a first input signal,

wherein the other of the source and the drain of the eleventh transistor is supplied with an inverted signal of the first input signal,

wherein each of the other of the source and the drain of the second transistor and the other of the source and the drain of the twelfth transistor is supplied with a second input signal,

wherein each of the other of the source and the drain of the fourth transistor and the other of the source and the drain of the tenth transistor is supplied with an inverted signal of the second input signal,

wherein the other of the source and the drain of the third transistor is supplied with a third input signal, and

wherein the other of the source and the drain of the ninth transistor including an oxide semiconductor is supplied with an inverted signal of the third input signal.

13. The logic circuit according to claim 7, wherein the logic circuit is an XOR circuit.

14. The logic circuit according to claim 7, wherein the logic circuit is a MUX circuit.

15. A semiconductor integrated circuit comprising the logic circuit according to claim 7.

16. A logic circuit comprising:

a first node and a second node;

a comparator configured to compare potentials of the first node and the second node;

a charge retaining portion electrically connected to the comparator via the first node and the second node; and

an output-node-potential determining portion electrically connected to the charge retaining portion,

wherein the charge retaining portion comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor,

wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor,

wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the first transistor,

wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a gate of the eighth transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first node,

wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the first node,

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor, and

wherein the output-node-potential determining portion is electrically connected to the other of the source and the drain of the sixth transistor and the other of the source and the drain of the eighth transistor.

17. The logic circuit according to claim 16,

wherein the comparator includes a first p-channel transistor, a second p-channel transistor, a third p-channel transistor and a fourth p-channel transistor,

wherein the output-node-potential determining portion comprises a n-channel transistor whose source or drain is electrically connected to the charge retaining portion,

wherein a source or a drain of the first p-channel transistor and a source or a drain of the second p-channel transistor are electrically connected to the first node,

wherein a source or a drain of the third p-channel transistor and a source or a drain of the fourth p-channel transistor are electrically connected to the second node,

wherein a gate of the second p-channel transistor is electrically connected to the second node,

wherein a gate of the third p-channel transistor is electrically connected to the first node, and

wherein each of a gate of the first p-channel transistor, a gate of the fourth p-channel transistor and a gate of the n-channel transistor is supplied with a clock signal.

18. The logic circuit according to claim 16,

wherein the comparator includes a first n-channel transistor, a second n-channel transistor, a third n-channel transistor and a fourth n-channel transistor,

wherein the output-node-potential determining portion comprises a p-channel transistor,

wherein a source or a drain of the first n-channel transistor and a source or a drain of the second n-channel transistor are electrically connected to the first node,

wherein a source or a drain of the third n-channel transistor and a source or a drain of the fourth n-channel transistor are electrically connected to the second node,

wherein a gate of the second n-channel transistor is electrically connected to the second node,

wherein a gate of the third n-channel transistor is electrically connected to the first node, and

wherein each of a gate of the first n-channel transistor, a gate of the fourth n-channel transistor and a gate of the p-channel transistor is supplied with a clock signal.

19. The logic circuit according to claim 16, wherein the logic circuit is an XOR circuit.

20. The logic circuit according to claim 16, wherein the logic circuit is a MUX circuit.

21. A semiconductor integrated circuit comprising the logic circuit according to claim 16.