Loop filter for current-controlled-oscillator-based phase locked loop

• US 8,508,267 B1
• Filed: 01/24/2012
• Issued: 08/13/2013
• Est. Priority Date: 01/24/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sreekiran, Samala
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/356,654
• Publication Number:
  US 20130187691A1
• Time in Patent Office: 567 Days
• Field of Search: 327/147, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A loop filter of a phase-locked loop (PLL) that uses a current-controlled oscillator (CCO) includes a capacitor, a voltage-to-current (V-to-I) converter, and a charge pump. The input node of the loop filter receives a first current from an external charge pump. The combination of the capacitor and the V-to-I converter generates a first component of the output current of the loop filter based on the first current. The charge pump of the loop filter generates a second component of the output current. The loop filter is implemented without the need for a zero-frequency-determining resistor, the resistor instead being realized by the product of the first current, the second component of the output current and the transconductance of the V-to-I converter. Phase noise reduction in the PLL, as well as implementation of the loop filter with a smaller area, are thus made possible.

Claims

1. A loop filter of a phase-locked loop (PLL), the loop filter comprising:

a first capacitor coupled between an input node of the loop filter and a constant reference potential, the first capacitor to receive a first current generated by a first charge pump external to the loop filter, the first current generating a first voltage at the input node;

a voltage-to-current converter (V-to-I) circuit coupled to receive the first voltage and to generate a first component of an output current at an output node of the loop filter;

a second charge pump to generate a second component of the output current at the output node, wherein the output current is the sum of the first component and the second component.

2. The loop filter of claim 1, wherein a zero frequency of a transfer function of the loop filter is determined by each of a capacitance of the first capacitor, a ratio of the second component of the output current and the first current, and a transconductance of the V-to-I converter,

wherein the ratio of the second component of the output current and the product of the first current and the transconductance represents a resistance, the resistance and the capacitance together determining the zero frequency.

3. The loop filter of claim 2, wherein the second charge pump generates the second component of the output current with a same polarity as the first current in all time intervals.

4. The loop filter of claim 1, wherein the V-to-I circuit comprises:

a first transistor, wherein a control terminal of the first transistor is coupled to the input node, wherein a first current terminal of the first transistor is coupled to the constant reference potential;

an active cascode circuit, wherein a first terminal of the active cascode circuit is coupled to a second current terminal of the first transistor, wherein a second terminal of the active cascode circuit is the output terminal.

5. The loop filter of claim 4, further comprising:

a second transistor; and

a low-pass filter,

wherein a control terminal of the second transistor is coupled to the input node via the low-pass filter, a first current terminal of the second transistor is coupled to the constant reference potential, and a second current terminal of the second transistor is coupled to the second current terminal of the first transistor.

6. The loop filter of claim 5, further comprising a second capacitor, wherein the second capacitor is coupled between the output node and the constant reference potential.

7. A phase locked loop (PLL) comprising:

a phase detector to receive a reference clock and a feedback clock as inputs, and to generate an error signal proportional to a phase difference between the reference clock and the feedback clock;

a loop filter to generate an output current by low-pass filtering the error signal;

a current controlled oscillator (CCO) to generate an output clock with a frequency proportional to the output current; and

a frequency divider to generate the feedback clock from the output clock,

wherein the loop filter comprises;

a first capacitor coupled between an input node of the loop filter and a first constant reference potential, the first capacitor to receive the error signal, the error signal generating a first voltage at the input node;

a voltage-to-current converter (V-to-I) circuit coupled to receive the first voltage and to generate a first component of the output current;

a first charge pump to generate a second component of the output current, wherein the output current is the sum of the first component and the second component, wherein the output current is provided at an output node of the loop filter.

8. The PLL of claim 7, wherein the V-to-I circuit comprises:

an operational amplifier (OPAMP);

a first N-type MOS transistor (NMOS) transistor, wherein a control terminal of the first NMOS transistor is coupled to the input node, wherein a first current terminal of the first NMOS transistor is coupled to the first constant reference potential; and

a current mirror pair comprising a first P-type MOS (PMOS) transistor and a second PMOS transistor, wherein a control terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to an output terminal of the OPAMP, wherein a first current terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a second constant reference potential, wherein a second current terminal of the first PMOS transistor is coupled to a second current terminal of the first NMOS transistor, wherein a first input terminal of the OPAMP is coupled to the second current terminal of the first NMOS transistor, and wherein a second current terminal of the second PMOS transistor is coupled to each of a second input terminal of the OPAMP and the output node.

9. The PLL of claim 8, wherein the V-to-I circuit further comprises:

a second NMOS transistor, wherein a control terminal of the second NMOS transistor is coupled to the input node via a resistor, wherein a first current terminal of the second NMOS transistor is coupled to the first constant reference potential, wherein a second current terminal of the second NMOS transistor is coupled to the second current terminal of the first NMOS transistor, and wherein a capacitor is coupled between the control terminal of the second NMOS transistor and the first constant reference potential.

10. The PLL of claim 9, wherein the error signal is a first current, wherein the first charge pump generates the second component of the output current with a same polarity as the first current in all time intervals.

11. The PLL of claim 7, wherein the PLL is comprised in an integrated circuit (IC).