Three dimensional inductor, transformer and radio frequency amplifier

• US 8,508,301 B2
• Filed: 11/11/2011
• Issued: 08/13/2013
• Est. Priority Date: 10/08/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Jonghae, Gu, Shiqun, Henderson, Brian Matthew, Toms, Thomas R., Chua-Eoan, Lew G., Bazarjani, Seyfollah S., Nowak, Matthew
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US13/294,351
• Publication Number:
  US 20120056680A1
• Time in Patent Office: 641 Days
• Field of Search: 330/307, 330/188, 330/195
• US Class Current: 330/307
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 19/04 Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range resonant circuits H03H
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

Claims

1. A three dimensional on-chip radio frequency amplifier comprising:

a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor;

a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor; and

an on-chip transistor comprising a gate, a drain and a source;

wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first segments in a first metal layer;

a plurality of second segments in a second metal layer;

a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the second metal layer; and

a plurality of through vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input;

the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground;

the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier;

the first inductor input of the second on-chip inductor being coupled to the gate of the on-chip transistor;

the first inductor input of the third on-chip inductor being coupled to the drain of the on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier;

the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground; and

the source of the on-chip transistor being coupled to ground.

2. The on-chip radio frequency amplifier of claim 1, wherein the first metal layer is located in a back-end-of-line section of the chip.

3. The on-chip radio frequency amplifier of claim 1, wherein the second metal layer is located in a redistributed design layer of the chip.

4. The on-chip radio frequency amplifier of claim 3, wherein the first metal layer is located in a back-end-of-line section of the chip.

5. A three dimensional on-chip radio frequency amplifier comprising:

a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor;

a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor;

a fifth on-chip inductor including a first inductor input and a second inductor input;

a sixth on-chip inductor including a first inductor input and a second inductor input;

a first on-chip transistor comprising a gate, a drain and a source; and

a second on-chip transistor including a gate, a drain and a source;

wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first segments in a first metal layer;

a plurality of second segments in a second metal layer;

a first inductor input and a second inductor input, the first and second inductor inputs of each of the first, second, third and fourth on-chip inductors being located in one of the first metal layer and the second metal layer; and

a plurality of through vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input of each of the first, second, third and fourth on-chip inductors;

the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground;

the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier;

the first inductor input of the second on-chip inductor being coupled to the gate of the first on-chip transistor;

the first inductor input of the third on-chip inductor being coupled to the drain of the second on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier;

the gate of the second on-chip transistor being coupled to the drain of the first on-chip transistor;

the first inductor inputs of the fifth and sixth on-chip inductors being coupled to a supply voltage;

the second inductor input of the fifth on-chip inductor being coupled to the drain of the first on-chip transistor;

the second inductor input of the sixth on-chip inductor being coupled to the drain of the second on-chip transistor;

the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground;

the source of the first and second on-chip transistors being coupled to ground.

6. The on-chip radio frequency amplifier of claim 5, wherein the first metal layer is located in a back-end-of-line section of the chip.

7. The on-chip radio frequency amplifier of claim 5, wherein the second metal layer is located in a redistributed design layer of the chip.

8. The on-chip radio frequency amplifier of claim 7, wherein the first metal layer is located in a back-end-of-line section of the chip.

9. The on-chip radio frequency amplifier of claim 5, further comprising:

a first capacitor and a second capacitor;

wherein the first inductor input of the second on-chip inductor is coupled to the gate of the first on-chip transistor through the first capacitor; and

the first inductor input of the third on-chip inductor is coupled to the drain of the second on-chip transistor through the second capacitor.

10. The on-chip radio frequency amplifier of claim 9, further comprising:

a resistor, the gate of the first on-chip transistor being coupled to the supply voltage through the resistor.

11. The on-chip radio frequency amplifier of claim 5, wherein:

the fifth on-chip inductor comprises a plurality of first segments in the first metal layer, a plurality of second segments in the second metal layer and a plurality of through vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input of the fifth on-chip inductor, the first and second inductor inputs of the fifth on-chip inductor being located in one of the first metal layer and the second metal layer; and

the sixth on-chip inductor comprises a plurality of first segments in the first metal layer, a plurality of second segments in the second metal layer and a plurality of through vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input of the sixth on-chip inductor, the first and second inductor inputs of the sixth on-chip inductor being located in one of the first metal layer and the second metal layer.

12. A three dimensional on-chip radio frequency amplifier comprising:

a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor;

a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor; and

an on-chip transistor comprising a gate, a drain and a source;

wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first conducting means in a first metal layer;

a plurality of second conducting means in a second metal layer;

a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the second metal layer; and

a plurality of through vias coupling the plurality of first conducting means and the plurality of second conducting means to form a continuous, non-intersecting path between the first inductor input and the second inductor input;

the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground;

the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier;

the first inductor input of the second on-chip inductor being coupled to the gate of the on-chip transistor;

the first inductor input of the third on-chip inductor being coupled to the drain of the on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier;

the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground; and

the source of the on-chip transistor being coupled to ground.

13. The on-chip radio frequency amplifier of claim 12, wherein the first metal layer is located in a back-end-of-line section of the chip.

14. The on-chip radio frequency amplifier of claim 12, wherein the second metal layer is located in a redistributed design layer of the chip.

15. The on-chip radio frequency amplifier of claim 14, wherein the first metal layer is located in a back-end-of-line section of the chip.

16. A three dimensional on-chip radio frequency amplifier comprising:

a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor;

a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor;

a fifth on-chip inductor including a first inductor input and a second inductor input;

a sixth on-chip inductor including a first inductor input and a second inductor input;

a first on-chip transistor comprising a gate, a drain and a source; and

a second on-chip transistor including a gate, a drain and a source;

wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first conducting means in a first metal layer;

a plurality of second conducting means in a second metal layer;

a first inductor input and a second inductor input, the first and second inductor inputs of each of the first, second, third and fourth on-chip inductors being located in one of the first metal layer and the second metal layer; and

a plurality of through vias coupling the plurality of first conducting means and the plurality of second conducting means to form a continuous, non-intersecting path between the first inductor input and the second inductor input of each of the first, second, third and fourth on-chip inductors;

the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground;

the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier;

the first inductor input of the second on-chip inductor being coupled to the gate of the first on-chip transistor;

the first inductor input of the third on-chip inductor being coupled to the drain of the second on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier;

the gate of the second on-chip transistor being coupled to the drain of the first on-chip transistor;

the first inductor inputs of the fifth and sixth on-chip inductors being coupled to a supply voltage;

the second inductor input of the fifth on-chip inductor being coupled to the drain of the first on-chip transistor;

the second inductor input of the sixth on-chip inductor being coupled to the drain of the second on-chip transistor;

the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground;

the source of the first and second on-chip transistors being coupled to ground.

17. The on-chip radio frequency amplifier of claim 16, wherein the first metal layer is located in a back-end-of-line section of the chip.

18. The on-chip radio frequency amplifier of claim 16, wherein the second metal layer is located in a redistributed design layer of the chip.

19. The on-chip radio frequency amplifier of claim 18, wherein the first metal layer is located in a back-end-of-line section of the chip.

20. The on-chip radio frequency amplifier of claim 16, wherein:

the fifth on-chip inductor comprises a plurality of first conducting means in the first metal layer, a plurality of second conducting means in the second metal layer and a plurality of through vias coupling the plurality of first conducting means and the plurality of second conducting means to form a continuous, non-intersecting path between the first inductor input and the second inductor input of the fifth on-chip inductor, the first and second inductor inputs of the fifth on-chip inductor being located in one of the first metal layer and the second metal layer; and

the sixth on-chip inductor comprises a plurality of first conducting means in the first metal layer, a plurality of second conducting means in the second metal layer and a plurality of through vias coupling the plurality of first conducting means and the plurality of second conducting means to form a continuous, non-intersecting path between the first inductor input and the second inductor input of the sixth on-chip inductor, the first and second inductor inputs of the sixth on-chip inductor being located in one of the first metal layer and the second metal layer.

21. A method for forming a three dimensional on-chip radio frequency amplifier, comprising:

forming a first on-chip transformer comprising a first on-chip inductor and a second on- chip inductor and a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor, wherein the first, second, third and fourth on-chip inductors are not physically coupled to one another except through ground, and wherein the first, second, third and fourth on- chip inductors each comprise a plurality of first segments in a first metal layer, a plurality of second segments in a second metal layer, a first inductor input located in one of the first metal layer and the second metal layer, a second inductor input located in one of the first metal layer and the second metal layer, and a plurality of through vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input;

inductively coupling the first on-chip inductor to the second on-chip inductor and inductively coupling the third on-chip inductor to the fourth on-chip inductor;

coupling the first inductor input of the first on-chip inductor to an input of the on-chip radio frequency amplifier, coupling the first inductor input of the second on-chip inductor to a gate of an on-chip transistor, coupling the first inductor input of the third on-chip inductor to a drain of the on-chip transistor, and coupling the first inductor input of the fourth on-chip inductor to an output of the on-chip radio frequency amplifier; and

coupling the second inductor input of the first, second, third and fourth on-chip inductors and a source of the on-chip transistor to ground.

22. A method for forming a three dimensional on-chip radio frequency amplifier, comprising:

forming a first on-chip transformer comprising a first on-chip inductor and a second on- chip inductor and a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor, wherein the first, second, third and fourth on-chip inductors are not physically coupled to one another except through ground, and wherein the first, second, third and fourth on- chip inductors each comprise a plurality of first segments in a first metal layer, a plurality of second segments in a second metal layer, a first inductor input located in one of the first metal layer and the second metal layer, a second inductor input located in one of the first metal layer and the second metal layer, and a plurality of through vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input of each of the first, second, third and fourth on-chip inductors;

forming a fifth on-chip inductor and a sixth on-chip inductor, wherein the fifth and sixth on-chip inductors each include a first inductor input and a second inductor input;

inductively coupling the first on-chip inductor to the second on-chip inductor and inductively coupling the third on-chip inductor to the fourth on-chip inductor;

coupling the first inductor input of the first on-chip inductor to an input of the on-chip radio frequency amplifier, coupling the first inductor input of the second on-chip inductor to a gate of a first on-chip transistor, coupling the first inductor input of the third on-chip inductor and the second inductor input of the sixth on-chip inductor to a drain of a second on-chip transistor, coupling the first inductor input of the fourth on-chip inductor to an output of the on- chip radio frequency amplifier, and coupling a gate of the second on-chip transistor and the second inductor input of the fifth on-chip inductor to a drain of the first on-chip transistor;

coupling the first inductor input of the fifth on-chip inductor and the first inductor input of the sixth on-chip inductor to a supply voltage; and

coupling the second inductor input of the first, second, third and fourth on-chip inductors and a source of the first and second on-chip transistors to ground.