Semiconductor device and driving method of semiconductor device

• US 8,508,967 B2
• Filed: 09/01/2011
• Issued: 08/13/2013
• Est. Priority Date: 09/03/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/223,490
• Publication Number:
  US 20120057396A1
• Time in Patent Office: 712 Days
• Field of Search: 365/51
• US Class Current: 365/51
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is provided with both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small) and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed). The peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion; thus, the area and size of the semiconductor device can be decreased.

Claims

1. A semiconductor device comprising:

first to fourth driver circuits; and

a memory cell array comprising a plurality of memory cells arranged in a matrix over the first to fourth driver circuits,

wherein one of the plurality of memory cells comprises;

a transistor comprising a gate electrode, a source electrode, a drain electrode, an oxide semiconductor layer, and a gate insulating layer; and

a capacitor comprising a pair of electrode layers and a dielectric layer therebetween, wherein one of the pair of electrode layers comprises the source electrode or the drain electrode, and the dielectric layer comprises the gate insulating layer,

wherein the first driver circuit and the second driver circuit are arranged so as to be substantially symmetrical with respect to a center point of the memory cell array,

wherein the third driver circuit and the fourth driver circuit are arranged so as to be perpendicular to the first driver circuit and the second driver circuit, and

wherein the third driver circuit and the fourth driver circuit are arranged so as to be substantially symmetrical with respect to the center point of the memory cell array.

2. The semiconductor device according to claim 1, wherein the first to fourth driver circuits are covered with the memory cell array.

3. The semiconductor device according to claim 1, wherein the first and second driver circuits each comprise a column decoder and a sense amplifier portion, and the third and fourth driver circuits each comprise a row decoder.

4. The semiconductor device according to claim 1, wherein the number of wirings connected to the first driver circuit and the memory cell array is equal to the number of wirings connected to the second driver circuit and the memory cell array.

5. The semiconductor device according to claim 1, wherein the number of wirings connected to the third driver circuit and the memory cell array is equal to the number of wirings connected to the fourth driver circuit and the memory cell array.

6. The semiconductor device according to claim 1, wherein the first to fourth driver circuits comprise a material other than an oxide semiconductor.

7. The semiconductor device according to claim 1, wherein the first to fourth driver circuits comprise silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide.

8. The semiconductor device according to a claim 1, wherein the transistor comprises a semiconductor material having an energy gap of more than 3 eV.

9. The semiconductor device according to a claim 1, wherein the first to fourth driver circuits are provided on an SOI substrate.

10. The semiconductor device according to a claim 1, wherein the first to fourth driver circuits are provided under a peripheral portion of the memory cell array.

11. A semiconductor device comprising:

first to fourth driver circuits; and

a memory cell array comprising a plurality of memory cells arranged in a matrix over the first to fourth driver circuits,

wherein one of the plurality of memory cells comprises;

a transistor comprising a gate electrode, a source electrode, a drain electrode, an oxide semiconductor layer, and a gate insulating layer; and

a capacitor comprising a pair of electrode layers and a dielectric layer therebetween, wherein one of the pair of electrode layers comprises the source electrode or the drain electrode, and the dielectric layer comprises the gate insulating layer,

wherein an area of the first driver circuit differs from an area of the second driver circuit,

wherein the third driver circuit and the fourth driver circuit are arranged so as to be perpendicular to the first driver circuit and the second driver circuit, and

wherein an area of the third driver circuit differs from an area of the fourth driver circuit.

12. The semiconductor device according to claim 11, wherein the first to fourth driver circuits are covered with the memory cell array.

13. The semiconductor device according to claim 11, wherein the first and second driver circuits each comprise a column decoder and a sense amplifier portion, and the third and fourth driver circuits each comprise a row decoder.

14. The semiconductor device according to claim 11, wherein the number of wirings connected to the first driver circuit and the memory cell array differs from the number of wirings connected to the second driver circuit and the memory cell array.

15. The semiconductor device according to claim 11, wherein the number of wirings connected to the third driver circuit and the memory cell array differs from the number of wirings connected to the fourth driver circuit and the memory cell array.

16. The semiconductor device according to claim 11, wherein the first to fourth driver circuits comprise a material other than an oxide semiconductor.

17. The semiconductor device according to claim 11, wherein the first to fourth driver circuits comprise silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide.

18. The semiconductor device according to a claim 11, wherein the transistor comprises a semiconductor material having an energy gap of more than 3 eV.

19. The semiconductor device according to a claim 11, wherein the first to fourth driver circuits are provided on an SOI substrate.

20. The semiconductor device according to a claim 11, wherein the first to fourth driver circuits are provided under a peripheral portion of the memory cell array.