Apparatus for variable resistive memory punchthrough access method

• US 8,508,981 B2
• Filed: 05/23/2012
• Issued: 08/13/2013
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Khoury, Maroun Georges, Liu, Hongyue, Lee, Brian, Carter, Andrew John Gjevre
• Primary Examiner(s): Lam, David
• Application Number:
  US13/478,174
• Publication Number:
  US 20120230084A1
• Time in Patent Office: 447 Days
• Field of Search: 365/148, 365/171, 365/173, 365/158, 365/185.18
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

Claims

1. A method comprising:

applying a voltage across a source region and a drain region of a transistor that is sufficient to merge a source depletion region and a drain depletion region of the transistor and conduct a write current through the transistor;

switching a variable resistive data cell from a high resistance state to a low resistance state by passing the write current through the variable resistive data cell in a first direction.

2. The method according to claim 1, further comprising switching the variable resistive data cell from the low resistance state to the high resistance state by passing the write current through the variable resistive data cell in a second direction opposing the first direction.

3. The method according to claim 1, wherein the transistor is a NMOS transistor or a PMOS transistor.

4. The method according to claim 1, wherein the variable resistive data cell is a magnetic tunnel junction data cell.

5. The method according to claim 1, wherein the write current in the first direction has about the same magnitude as the write current in the second direction.

6. The method according to claim 3, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

7. The method according to claim 1, further comprising passing a read current through the variable resistive data cell by activating a gate of the transistor.

8. The method according to claim 1, further comprising passing a read current through the variable resistive data cell, the read current formed by applying a voltage across a source region and a drain region of a transistor that is sufficient to merge a source depletion region and a drain depletion region of the transistor and conduct the read current through the transistor.

9. The method according to claim 1, wherein the write current in the first direction and the write current in the second direction is formed by a voltage difference across a source region and drain region of the transistor having a magnitude equal to or greater than a punchthrough voltage for the transistor.

10. A method comprising:

switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the variable resistive data cell in a first direction, the write current passing through the transistor in punchthrough mode.

11. The method according to claim 10, further comprising switching the variable resistive data cell from the low resistance state to the high resistance state by passing the write current through the variable resistive data cell in a second direction opposing the first direction, the write current provided by the transistor operating in punchthrough mode.

12. The method according to claim 10, wherein the transistor is a NMOS transistor or a PMOS transistor.

13. The method according to claim 10, wherein the variable resistive data cell is a magnetic tunnel junction data cell.

14. The method according to claim 10, wherein the write current in the first direction has about the same magnitude as the write current in the second direction.

15. The method according to claim 13, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

16. The method according to claim 10, further comprising passing a read current through the variable resistive data cell by activating a gate of the transistor.

17. A method comprising:

applying a voltage across a source region and a drain region of a first transistor that is sufficient to merge a source depletion region and a drain depletion region of the first transistor and conduct a write current through the first transistor;

activating a common transistor to allow the write current to pass through the common transistor, the common transistor electrically coupled to a source line and the first variable resistive data cell, the common transistor electrically coupled to a second variable resistive data cell.

18. The method according to claim 17 wherein the first and second variable resistive data cells are spin-transfer torque data cells.

19. The method according to claim 17 wherein the write current selectively passes through the first and second variable resistive data cells.

20. The method according to claim 17 wherein the common transistor is electrically connected to three or more variable resistive data cells.