Nonvolatile static random access memory cell and memory circuit

• US 8,508,983 B2
• Filed: 09/13/2011
• Issued: 08/13/2013
• Est. Priority Date: 06/15/2011
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Min-Chuan, Chiu, Pi-Feng, Sheu, Shyh-Shyuan
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/230,865
• Publication Number:
  US 20120320658A1
• Time in Patent Office: 700 Days
• Field of Search: 365/154, 365/156, 365/148, 365/158, 365/163, 365/171, 365/173, 365/185.07, 365/185.08
• US Class Current: 365/154
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell

Abstract

A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.

Claims

1. A non-volatile static random access memory cell, comprising:

a static random access circuit, having a first terminal and a second terminal respectively having a first voltage and a second voltage, wherein stored data is determined by the first voltage and the second voltage;

a first storage device, having a first connection terminal and a second connection terminal, wherein the first connection terminal of the first storage device is coupled to the first terminal of the static random access circuit;

a second storage device, having a first connection terminal and a second connection terminal, wherein the first connection terminal of the second storage device is coupled to the second terminal of the static random access circuit; and

a switch unit, respectively coupled to the second connection terminal of the first storage device and the second connection terminal of the second storage device, wherein the switch unit is turned on/off in response to a switching signal, and when the switch unit is turned on, the two second connection terminals are directly conducted to a bit line or a complementary bit line corresponding to the bit line by the switching unit, wherein the switching signal is different from a word line signal.

2. The non-volatile static random access memory cell as claimed in claim 1, wherein the static random access circuit comprises:

a latch circuit unit;

a first transistor, having a first electrode, a second electrode and a gate, wherein the first electrode is coupled to the bit line, the second electrode is coupled to the latch circuit unit, and the gate is coupled to a word line; and

a second transistor, having a first electrode, a second electrode and a gate, wherein the first electrode is coupled to the complementary bit line, the second electrode is coupled to the latch circuit unit, and the gate is coupled to the word line.

3. The non-volatile static random access memory cell as claimed in claim 2, wherein the latch circuit unit comprises two inverters.

4. The non-volatile static random access memory cell as claimed in claim 1, wherein the switch unit comprises a single switch device coupled between the second connection terminals of the first storage device and the second storage device, and the bit line or the complementary bit line.

5. The non-volatile static random access memory cell as claimed in claim 4, wherein the switch device is a transistor switch or a diode switch.

6. The non-volatile static random access memory cell as claimed in claim 1, wherein the first storage device and the second storage device respectively have two electrical states under two different bias states for storing data.

7. The non-volatile static random access memory cell as claimed in claim 1, wherein the first storage device and the second storage device are resistive-switching devices, phase-change memory device or magnetoresistive random access memory devices.

8. The non-volatile static random access memory cell as claimed in claim 1, wherein the static random access circuit comprises:

a latch circuit unit;

having the first terminal and the second terminal;

a first transistor, having a first electrode, a second electrode and a gate, wherein the first electrode is coupled to the bit line, the second electrode is coupled to the first terminal of the latch circuit unit, and the gate is coupled to a word line; and

a second transistor, having a first electrode, a second electrode and a gate, wherein the first electrode is coupled to the complementary bit line, the second electrode is coupled to the second terminal of the latch circuit unit, and the gate is coupled to the word line.

9. The non-volatile static random access memory cell as claimed in claim 1, wherein the switch unit comprises:

a first switch device, coupled between the second connection terminal of the first storage device and the bit line, or coupled between the second connection terminal of the second storage device and the complementary bit line; and

a second switch device, coupled between the second connection terminals of the first storage device and the second storage devices, the second switch device and the first switch device are simultaneously turned on or turned off in response to the switching signal.

10. The non-volatile static random access memory cell as claimed in claim 9, wherein the first switch device and the second switch device are transistor switches or diode switches.

11. The non-volatile static random access memory cell as claimed in claim 9, wherein the first storage device and the second storage device respectively have two electrical states under two different bias states for storing data.

12. A non-volatile static random access memory circuit, comprising:

a plurality of first memory cells, the same to the non-volatile static random access memory cell as claimed in claim 4, wherein the switch device is connected to the bit line; and

a plurality of second memory cells, the same to the non-volatile static random access memory cell as claimed in claim 4, wherein the switch device is connected to the complementary bit line,

wherein the first memory cells and the second memory cells form a memory cell column between the bit line and the complementary bit line.

13. The non-volatile static random access memory circuit as claimed in claim 12, wherein the first memory cells and the second memory cells are arranged in alternation.

14. A non-volatile static random access memory circuit, comprising:

a plurality of first memory cells, the same to the non-volatile static random access memory cell as claimed in claim 9, wherein the switch device is connected to the bit line; and

a plurality of second memory cells, the same to the non-volatile static random access memory cell as claimed in claim 9, wherein the switch device is connected to the complementary bit line,

wherein the first memory cells and the second memory cells form a memory cell column between the bit line and the complementary bit line.

15. The non-volatile static random access memory circuit as claimed in claim 14, wherein the first memory cells and the second memory cells are arranged in alternation.

16. A non-volatile static random access memory circuit, comprising:

a plurality of first memory cells, the same to the non-volatile static random access memory cell as claimed in claim 1, wherein the switch device is connected to the bit line; and

a plurality of second memory cells, the same to the non-volatile static random access memory cell as claimed in claim 1, wherein the switch device is connected to the complementary bit line,

wherein the first memory cells and the second memory cells form a memory cell column between the bit line and the complementary bit line.