Methods, circuits, and systems to select memory regions

• US 8,509,021 B2
• Filed: 06/10/2011
• Issued: 08/13/2013
• Est. Priority Date: 05/21/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Scott
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US13/158,282
• Publication Number:
  US 20110246729A1
• Time in Patent Office: 795 Days
• Field of Search: 365/222, 365/200, 365/201, 365/230.03, 365/226, 365/227, 365/228, 365/229, 711/5
• US Class Current: 365/222
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.

Claims

1. A processor-based system comprising:

a processing apparatus operable to process data and to provide memory requests and addresses;

a plurality of memory devices;

a system controller in communication with the processing apparatus, the system controller operable to receive and transmit memory commands, addresses and data, and to receive memory requests corresponding to a first region of one or more of the plurality of memory devices, the system controller operable to communicate the memory requests to the one or more of the plurality of memory devices and transmit memory data from the one or more of the plurality of memory devices in response to at least one of the memory requests; and

a selection block configured to receive the memory requests corresponding to the first region of the one or more of the plurality of memory devices and to receive an input signal indicating a number of defective cells that are replaced by redundant cells in at least one region of the one or more of the plurality of memory devices selectable by the selection block relative to that of at least another region of the one or more of the plurality of memory devices selectable by the selection block, the selection block operable to map the memory requests to a second region of the one or more of the plurality of memory devices based on the input signal;

wherein the processing apparatus is configured to;

access a first memory device of the plurality of memory devices in response to a first memory request; and

access a second memory device of the plurality of memory devices in response to a second memory request, the first memory request preceding the second memory request; and

wherein;

the access of the second memory device occurs substantially contemporaneously with the access of the first memory device; and

the input signal is associated with at least one of the first and the second memory requests.

2. The processor-based system of claim 1, further comprising:

a user interface device in communication with the processing apparatus and configured to receive a user request;

a graphic controller in communication with the processing apparatus; and

a display apparatus in communication with the graphics controller;

wherein;

the graphics controller configured to;

receive a first plurality of bytes associated with the first memory request; and

output the first plurality of bytes to the display apparatus in response to the user request; and

the input signal is generated responsive to the user request.

3. The processor-based system of claim 2, further comprising a data storage device in communication with the processing apparatus, the data storage device configured to store the first plurality of bytes.

4. The processor-based system of claim 2, further comprising a data storage device in communication with the processing apparatus, the data storage device configured to provide a second plurality of bytes associated with the second memory request.

5. The processor-based system of claim 1, further comprising:

a user interface device in communication with the processing apparatus and configured to receive a user request; and

an output device in communication with the processing apparatus and configured to;

receive a first plurality of bytes associated with the first memory request; and

generate a user-readable output corresponding to the first plurality of bytes in response to the user request;

wherein the input signal is generated responsive to the user request.

6. The processor-based system of claim 1, further comprising a data storage device in communication with the processing apparatus;

wherein;

the processing apparatus is configured to receive a user request;

the data storage devices is configured to provide a first plurality of bytes associated with the first memory request in response to the user request; and

the input signal is generated responsive to the user request.

7. A processor-based apparatus comprising:

a first processing apparatus operable to process data and to provide memory requests and addresses;

a user interface apparatus in communication with the first processing apparatus and configured to receive a user request;

a system controller in communication with the first processing apparatus, the system controller operable to receive and transmit memory requests, addresses and data;

a plurality of memory devices operably coupled to the system controller;

a selection block configured to receive an address signal generated based at least in part on the user request, the address signal indicative of a region of the one or more of the plurality of memory devices, the selection block being operable to generate a selection signal to map the address signal indicative of the region of the one or more of the plurality of memory devices to a physical location of the one or more of the plurality of memory devices, the selection block further being operable to generate the selection signal on the basis of a number of defective cells that are replaced by redundant cells in the physical location of the one or more of the plurality of memory devices relative to that of at least one other region selectable by the selection block;

a second processing apparatus in communication with the first processing apparatus; and

a display apparatus in communication with the a second processing apparatus;

wherein the second processing apparatus is configured to;

receive a first plurality of bytes from associated with a first memory request of the memory requests; and

output the first plurality of bytes to the display apparatus in response to the user request.

8. The processor-based apparatus of claim 7, wherein the first processing apparatus is configured to:

access a first memory device in response to the first memory request; and

access a second memory device of the plurality of memory devices in response to a second memory request of the memory requests, the first memory request preceding the second memory request; and

wherein;

the access of the second memory device occurs substantially contemporaneously with the access of the first memory device; and

the address signal is associated with at least one of the first and the second memory requests.

9. The processor-based apparatus of claim 8, further comprising a data storage device in communication with the first processing apparatus, the data storage device configured to store a second first plurality of bytes associated with the second memory request.

10. The processor-based apparatus of claim 7, further comprising an output device in communication with the processing apparatus, the output device configured to:

receive a second plurality of bytes associated with a second memory request of the memory requests; and

generate a user-readable output corresponding to the second plurality of bytes in response to the user request.

11. The processor-based apparatus of claim 10, further comprising a data storage device in communication with the first processing apparatus, the data storage device configured to provide the second plurality of bytes.

12. The processor-based apparatus of claim 7, further comprising a data storage device in communication with the first processing apparatus, the data storage device configured to store the first plurality of bytes in response to the user request.

13. The processor-based apparatus of claim 7, wherein the second processing apparatus comprises a graphics controller apparatus.

14. A processor-based apparatus comprising:

a first processing apparatus operable to process data and to provide memory commands and addresses;

a user interface apparatus in communication with the first processing apparatus and configured to generate a first user interface request;

a plurality of memory devices;

a system controller in communication with the first processing apparatus, the system controller operable to receive and transmit memory commands, addresses and data, and to receive memory requests corresponding to a first region of one or more of the plurality of memory devices, the system controller operable to communicate the memory requests to the one or more of the plurality of memory devices and transmit memory data from the one or more of the plurality of memory devices in response to at least one of the memory requests;

a selection block configured to receive the memory requests corresponding to the first region of the one or more of the plurality of memory devices and to receive an input signal indicating a number of defective cells that are replaced by redundant cells in at least one region of the one or more of the plurality of memory devices selectable by the selection block relative to that of at least another region of the one or more of the plurality of memory devices selectable by the selection block, the selection block operable to map the memory requests to a second region of the one or more of the plurality of memory devices based on the input signal; and

a data storage device in communication with the first processing apparatus, the data storage device configured to provide a first plurality of bytes associated with a first memory request of the memory requests, based at least in part on the first user interface request.

15. The processor-based apparatus of claim 14, further comprising:

an output device in communication with the first processing apparatus and configured to;

receive the first plurality of bytes; and

generate a user-readable output corresponding to the first plurality of bytes in response to a second user interface request.

16. The processor-based apparatus of claim 15, wherein the first user interface request comprises the second user interface request.

17. The processor-based apparatus of claim 14, further comprising:

a second processing apparatus in communication with the first processing apparatus; and

a display apparatus in communication with the second processing apparatus;

wherein

the input signal is generated responsive to the user request; and

the second processing apparatus is configured to output a second plurality of bytes associated with a second memory request of the memory requests to the display apparatus, based at least in part on the user request.

18. The processor-based apparatus of claim 17, wherein the second processing apparatus comprises a graphics controller apparatus.

19. The processor-based apparatus of claim 17, wherein the second memory request is executed substantially contemporaneously with the first memory request.

20. A processor-based apparatus comprising:

a processing apparatus operable to process data and to provide memory commands and addresses;

a user interface apparatus in communication with the processing apparatus and configured to generate a plurality of user interface requests; and

a system controller in communication with the processing apparatus, the system controller operable to receive and transmit memory commands, addresses and data;

a plurality of memory devices in communication with the system controller;

a selection block configured to receive an address signal indicative of a region of the one or more of the plurality of memory devices, the selection block being operable to generate a selection signal to map the address signal indicative of the region of the one or more of the plurality of memory devices to a physical location of the one or more of the plurality of memory devices, the selection block further being operable to generate the selection signal on the basis of a number of defective cells that are replaced by redundant cells in the physical location of the one or more of the plurality of memory devices relative to that of at least one other region selectable by the selection block; and

an output device in communication with the processing apparatus and configured to receive a first plurality of bytes from a first memory device of the plurality of memory devices responsive to a first request of the plurality of user interface requests and to generate a user-readable output corresponding to the first plurality of bytes in response to a second request of the plurality of user interface requests.

21. The processor-based apparatus of claim 20, further comprising a data storage device in communication with the processing apparatus, the data storage device configured to provide a second plurality of bytes associated with a second memory device of the plurality of memory devices.

22. The processor-based apparatus of claim 20, further comprising a data storage device in communication with processing apparatus, the data storage device configured to store the first plurality of bytes, based at least in part on the user request.

23. The processor-based apparatus of claim 20, further comprising a data storage device in communication with the processing apparatus, the data storage device configured to provide a second plurality of bytes associated with a second memory request of the memory requests;

wherein;

the first plurality of bytes is associated with a first memory request; and

the second memory request is executed substantially contemporaneously with the first memory request.