System and method for multiplexing PDH and packet data

• US 8,509,143 B2
• Filed: 06/29/2010
• Issued: 08/13/2013
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Jao, Tjo San
• Primary Examiner(s): JAIN, RAJ K
• Application Number:
  US12/826,609
• Publication Number:
  US 20100265969A1
• Time in Patent Office: 1,141 Days
• Field of Search: None
• US Class Current: 370/324
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH
• CPC Class Codes: H04J 3/1623 Plesiochronous digital hierarchy [PDH]
• CPC Class Codes: H04J 3/247 ATM or packet multiplexing

Abstract

A method of efficiently combining data from at least a plurality of a first type of data source and a second type of data source. The method comprises synchronizing the plural first type of data sources to thereby generate a synchronized data rate, providing a frame having plural bit positions, assigning the synchronized first type of data in ones of the bit positions of the frame, and arranging the second type of data in the frame as a function of the synchronized data rate.

Claims

1. A method of transmitting data received from plural sources that are not synchronized with each other and a packet source as a single data stream comprising the steps of:

synchronizing data received from the plural sources that are not synchronized with each other to thereby generate a synchronized data rate;

providing a frame format comprising a plurality of frames, each frame having plural sub-frames, the number of which correlates to the number of plural sources that are not synchronized with each other and each sub-frame comprising a plurality of blocks, each block comprising;

at least one overhead bit position,

n bit positions of the synchronized data,

m bit positions of data received from the packet source arranged as a function of the synchronized data rate, and

a plurality of sub-blocks each having a bit position for the synchronized data or a bit position for data received from the packet source;

assigning the synchronized data and data received from the packet source in bit positions of the frame format; and

transmitting the assigned data as a single data stream.

2. The method of claim 1 further comprising the step of filling unassigned bit positions with packet data.

3. The method of claim 1 further comprising the steps of:

inserting a frame alignment word in bit positions of a first block of a first sub-frame; and

distributing synchronized data bits or data bits received from the packet source in unassigned overhead bit positions of other blocks.

4. The method of claim 1 wherein the plural sources that are not synchronized with each other include at least one of synchronous, asynchronous, and plesiochronous sources.

5. The method of claim 1 further comprising the step of sequentially bit interleaving the synchronized data bits and data bits received from the packet source in the frame format.

6. The method of claim 1 wherein the data received from the plural sources that are not synchronized with each other are synchronized by bit stuffing.

7. The method of claim 1 further comprising the step of distributing stuffing indication bits in unassigned overhead bit positions.

8. The method of claim 1 further comprising the step of distributing parity bits in unassigned overhead bit positions.

9. A system for transmitting data received from plural sources that are not synchronized with each other and a packet source as a single data stream, the system comprising:

means for synchronizing data received from the plural sources that are not synchronized with each other to thereby generate a synchronized data rate; and

means for providing a frame format comprising a plurality of frames, each frame having plural sub-frames, the number of which correlates to the number of plural sources that are not synchronized with each other and each sub-frame comprising a plurality of blocks, each block comprising;

at least one overhead bit position,

n bit positions of the synchronized data,

m bit positions of data received from the packet source arranged as a function of the synchronized data rate, and

a plurality of sub-blocks each having a bit position for the synchronized data or a bit position for data received from the packet source;

wherein the means for providing the frame format is further configured to assign the synchronized data and data received from the packet source in bit positions of the frame format; and

wherein the means for providing the frame format is further configured to transmit the assigned data as a single data stream.

10. The system of claim 9 wherein the means for providing the frame format is further configured to fill unassigned bit positions with packet data.

11. The system of claim 9 wherein the means for providing the frame format is further configured to:

insert a frame alignment word in bit positions of a first block of a first sub-frame; and

distribute synchronized data bits or data bits received from the packet source in unassigned overhead bit positions of other blocks.

12. The system of claim 9 wherein the plural sources that are not synchronized with each other include at least one of synchronous, asynchronous, and plesiochronous sources.

13. The system of claim 9 wherein the means for providing the frame format is further configured to sequentially bit interleave the synchronized data bits and data bits received from the packet source in the frame format.

14. The system of claim 9 wherein the data received from the plural sources that are not synchronized with each other are synchronized by bit stuffing.

15. The system of claim 9 wherein the means for providing the frame format is further configured to distribute stuffing indication bits in unassigned overhead bit positions.

16. The system of claim 9 wherein the means for providing the frame format is further configured to distribute parity bits in unassigned overhead bit positions.

17. A system for transmitting data received from plural sources that are not synchronized with each other and a packet source as a single data stream, the system comprising:

synchronizers configured to receive data from the plural sources that are not synchronized with each other to thereby generate a synchronized data rate; and

a multiplexer configured to provide a frame format comprising a plurality of frames, each frame having plural sub-frames, the number of which correlates to the number of plural sources that are not synchronized with each other and each sub-frame comprising a plurality of blocks, each block comprising;

at least one overhead bit position,

n bit positions of the synchronized data,

m bit positions of data received from the packet source arranged as a function of the synchronized data rate, and

a plurality of sub-blocks each having a bit position for the synchronized data or a bit position for data received from the packet source;

wherein the multiplexer is further configured to assign the synchronized data and data received from the packet source in bit positions of the frame format; and

wherein the multiplexer is further configured to transmit the assigned data as a single data stream.

18. The system of claim 17 wherein the multiplexer is further configured to fill unassigned bit positions with packet data.

19. The system of claim 17 wherein the multiplexer is further configured to:

insert a frame alignment word in bit positions of a first block of a first sub-frame, and

distribute synchronized data bits or data bits received from the packet source in unassigned overhead bit positions of other blocks.

20. The system of claim 17 wherein the plural sources that are not synchronized with each other include at least one of synchronous, asynchronous, and plesiochronous sources.

21. The system of claim 17 wherein the multiplexer is further configured to distribute stuffing indication bits in unassigned overhead bit positions.

22. The system of claim 17 wherein the multiplexer is further configured to distribute parity bits in unassigned overhead bit positions.