Memory system for portable telephone

• US 8,509,758 B2
• Filed: 01/20/2012
• Issued: 08/13/2013
• Est. Priority Date: 07/09/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shinohara, Takayuki, Kimura, Masatoshi
• Primary Examiner(s): Ajibade Akonai, Olumide T
• Assistant Examiner(s): Peaches, Randy
• Application Number:
  US13/355,207
• Publication Number:
  US 20120124278A1
• Time in Patent Office: 571 Days
• Field of Search: 455/418, 455/556.1, 455/575.2
• US Class Current: 455/418
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 16/13 File access structures, e.g. distributed indices arrangements of input from, or output to, record carriers G06F3/06
• CPC Class Codes: G06F 2207/7228 Random curve mapping, e.g. mapping to an isomorphous or projective curve
• CPC Class Codes: G06F 2213/3806 Mobile device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 7/725 over elliptic curves
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/3066 involving algebraic varieties, e.g. elliptic or hyper-elliptic curves
• CPC Class Codes: H04M 1/026 Details of the structure or mounting of specific components
• CPC Class Codes: H04M 1/6505 storing speech in digital form
• CPC Class Codes: H04M 1/72403 with means for local support of applications that increase the functionality
• CPC Class Codes: H04M 2201/36 Memories
• CPC Class Codes: H04M 2250/14 including a card reading device

Abstract

A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided.

Claims

1. A logic device, which is adapted to be coupled with a NAND flash memory configured for storing a program, music data and image data, and a volatile memory by a bus, comprising:

a memory interface unit for coupling with the NAND flash memory;

a central processing unit;

a baseband processing unit used for performing a signal processing on data received from an antenna; and

a media processing unit,

wherein when the data includes the music data or the image data, the data is transferred to the NAND flash memory,

wherein the central processing unit transfers the program stored in the NAND flash memory to the volatile memory, and fetches an instruction of the program from the volatile memory and executes the instruction, and

wherein the media processing unit decodes the music data stored in the NAND flash memory and outputs an audio signal via an audio terminal, and decodes the image data stored in the NAND flash memory and outputs a video signal via a display terminal.

2. The logic device according to claim 1,

wherein the program includes plural application programs, and the central processing unit transfers a corresponding application program based on an input information from an input device to the volatile memory and performs the corresponding application program transferred into the volatile memory.

3. The logic device according to claim 1,

wherein the central processing unit transfers a first program of the program from the NAND flash memory to the volatile memory in a power on sequence.

4. The logic device according to claim 3,

wherein the central processing unit transfers a second program of the program from the NAND flash memory to the volatile memory in accordance with a first signal from a key pad.

5. The logic device according to claim 3,

wherein the central processing unit transfers a third program of the program from the NAND flash memory to the volatile memory in accordance with a second signal received from the antenna.