Apparatus comprising artificial neuronal assembly

• US 8,510,244 B2
• Filed: 03/18/2010
• Issued: 08/13/2013
• Est. Priority Date: 03/20/2009
• Status: Active Grant

• Current Assignee: Irvine Sensors Corp., PFG Ip, LLC
• Original Assignee: ISC8 Incorporated
• Inventors: Carson, John C., Ozguz, Volkan
• Primary Examiner(s): Chaki, Kakali
• Assistant Examiner(s): COUGHLAN, PETER D
• Application Number:
  US12/661,537
• Publication Number:
  US 20100241601A1
• Time in Patent Office: 1,244 Days
• Field of Search: 706/27, 706/26
• US Class Current: 706/27
• CPC Class Codes: G06N 3/02 Neural networks

Abstract

An artificial synapse array and virtual neural space are disclosed.

More specifically, a cognitive sensor system and method are disclosed comprising a massively parallel convolution processor capable of, for instance, situationally dependent identification of salient features in a scene of interest by emulating the cortical hierarchy found in the human retina and visual cortex.

Claims

1. A cognitive sensor circuit for the emulation of the visual cortex of a human brain comprising:

a first supertile and a second supertile,

said first and second supertiles comprising a plurality of tiles and comprising a supertile processor, supertile memory and a supertile look up table,

said first supertile in electronic communication with said second supertile,

said tiles comprising a plurality of cells and comprising a tile processor, tile memory and a tile look up table,

selected ones of said tiles having a plurality of tile mesh outputs in electronic communication with an E, W, N and S neighboring tile of each of the selected tiles and with a supertile processor,

said cells comprising dedicated image memory and dedicated weight memory and convolution circuit means for performing a convolution kernel mask operation on an image data set representative of a scene,

selected ones of said cells having a plurality of cell mesh outputs in electronic communication with an E, W, N and S neighboring cell of the selected cells and a tile processor,

root processor circuit means for managing electronic communication between said cell mesh outputs, said tile mesh outputs or said supertile mesh outputs.

2. A method for emulating the visual cortex of a human brain comprising:

providing

a first supertile and a second supertile,

said first and second supertiles comprising a plurality of tiles and comprising a supertile processor, supertile memory and a supertile look up table,

said first supertile in electronic communication with said second supertile,

said tiles comprising a plurality of cells and comprising a tile processor, tile memory and a tile look up table,

selected ones of said tiles having a plurality of tile mesh outputs in electronic communication with an E, W, N and S neighboring tile of each of the selected tiles and with a supertile processor,

said cells comprising dedicated image memory and dedicated weight memory and convolution circuit means for performing a convolution kernel mask operation on an image data set representative of a scene,

selected ones of said cells having a plurality of cell mesh outputs in electronic communication with an E, W, N and S neighboring cell of the selected cells and a tile processor,

providing an image data set representative of a scene,

selecting one or more predetermined image data subsets from said image data set,

receiving said one or more image data subsets to a cell, and,

performing a concurrent convolution kernel mask operation in said cell on said image data subsets to provide a convolved cell output.