Low power digital interface

• US 8,510,485 B2
• Filed: 11/29/2007
• Issued: 08/13/2013
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wilson, Thomas James, Hori, Yutaka
• Primary Examiner(s): LEE, CHUN KUAN
• Application Number:
  US11/947,723
• Publication Number:
  US 20090063736A1
• Time in Patent Office: 2,084 Days
• Field of Search: 710 52- 61
• US Class Current: 710/61
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Claims

1. An master/slave serial peripheral interface (SPI) circuit comprising:

a master SPI interface including;

a master serial data output line;

a master serial data input line;

a master output interface clock line for transmitting interface clock signals; and

a slave SPI interface including;

a slave serial data input line connected to the master serial data output line;

a slave serial data output line connected to the master serial data input line;

a slave input interface clock line connected to the master output interface clock line for receiving the interface clock signals from the master SPI interface;

a buffer having a plurality of cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to output data bits in response to the interface clock signals;

a multiplexer having inputs connected to outputs of each of the plurality of cells of the buffer and an output provided as the slave serial data output line;

a demultiplexer having an input connected to receive the interface clock signals and outputs connected to the clock inputs of the plurality of cells;

a read pointer processing circuit for generating a read pointer;

the multiplexer connected to receive the read pointer for connecting as an input thereto only a selected output of a cell designated by the read pointer;

the demultiplexer connected to receive the read pointer for connecting the interface clock signals from the serial input interface clock line connected to the master output interface clock line to only a selected output thereof for feeding the interface clock signals to the clock input of the cell designated by the read pointer;

the clock input of the cell designated by the read pointer receiving the interface clock signals and outputting the data bits stored therein in synchronism with the interface clock signals,

wherein

the multiplexer outputs the data bits stored it the cell designated by the read pointer over the slave serial data output line in synchronism with the interface clock signals without reference to a dedicated high frequency clock signal.

2. The master/slave serial peripheral interface circuit as recited in claim 1 wherein the slave interface further comprises:

a bus data line input for receiving the data bits of a host device, and

a bus clock line input for receiving bus clock signals of the host device;

bus control circuitry operable to load the data bits into the buffer in response to bus clock signals.

3. The master/slave serial peripheral interface circuit as recited in claim 2 wherein the buffer comprises a plurality of FIFO cells.

4. The master/slave serial peripheral interface circuit as recited in claim 3 wherein each of the plurality of FIFO cells comprises a shift register responsive to the interface clock signals to shift data bits stored therein.

5. The master/slave serial peripheral interface circuit as recited in claim 4 wherein the bus control circuitry comprises:

a first demultiplexer having an input connected to receive the bus clock signals and outputs connect to clock inputs of the FIFO cells of the buffer;

a second demultiplexer having an input connected to the bus data line for receiving the data bits to be stored and outputs connected to the inputs of the plurality of cells;

a bus circuit for generating a write pointer;

the first demultiplexer connected to receive the write pointer for connecting the bus clock signals to only a designated output thereof for feeding the bus clock signals to the cell designated by the write pointer;

the second demultiplexer connected to receive the write pointer for connecting the data bits only to a designated output thereof for feeding the data bits to the cell designated by the write pointer.

6. The master/slave serial peripheral interface circuit as recited in claim 3 wherein the bus control circuitry comprises:

a first demultiplexer having an input connected to receive the bus clock signals and outputs connect to clock inputs of the FIFO cells of the buffer;

a second demultiplexer having an input connected to the bus data line for receiving the data bits to be stored and outputs connected to the inputs of the plurality of cells;

a bus circuit for generating a write pointer;

the first demultiplexer connected to receive the write pointer for connecting the bus clock signals to only a designated output thereof for feeding the bus clock signals to the cell designated by the write pointer;

the second demultiplexer connected to receive the write pointer for connecting the data bits only to a designated output thereof for feeding the data bits to the cell designated by the write pointer.

7. An electronic device comprising at least the slave SPI interface as recited in claim 1.

8. A portable audio player comprising at least the slave SPI interface as recited in claim 1.

9. A mobile telephone comprising at least the slave SPI interface as recited in claim 1.

10. A flash drive comprising at least the slave SPI interface as recited in claim 1.

11. A master/slave serial peripheral interface (SPI) circuit comprising:

a master SPI interface including;

a master serial data output line;

a master serial data input line;

an master output interface clock line for transmitting interface clock signals;

a slave SPI interface including;

a slave serial data input line connected to the master serial data output line;

a slave serial data output line connected to the master serial data input line;

a slave input interface clock line connected to the master output interface clock line for receiving the interface clock signals from the master SPI interface;

a buffer having a plurality of cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to store data bits therein and to output the data bits in response to the interface clock signals;

means for designating ones of the plurality of cells of the buffer;

means, responsive to the interface clock signals, for transmitting data bits from the designated ones of the plurality of cells to the slave serial data output line in synchronism with the interface clock signals received from the slave input interface clock line.

12. The master/slave serial peripheral interface circuit as recited in claim 11 wherein the slave SPI interface further comprises:

a bus data line of a bus of a host device comprising the slave SPI interface, and

a bus clock line of the bus configured to transmit bus clock signals;

bus control circuitry operable to load data into the buffer in response to bus clock signals.

13. The master/slave serial peripheral interface circuit as recited in claim 12 wherein the buffer comprises a plurality of FIFO cells.

14. The master/slave serial peripheral interface circuit as recited in claim 13 wherein each of the plurality of FIFO cells comprises a shift register responsive to the interface clock signals to shift data bits stored therein.

15. The master/slave serial peripheral interface circuit as recited in claim 11 wherein the buffer comprises a plurality of FIFO cells.

16. The master/slave serial peripheral interface circuit as recited in claim 15 wherein each of the plurality of FIFO cells comprises a shift register responsive to the interface clock signals to shift data bits stored therein.

17. An electronic device comprising at least the slave SPI interface as recited in claim 11.

18. A portable audio player comprising at least the slave SPI interface as recited in claim 11.

19. A mobile telephone comprising at least the slave SPI interface as recited in claim 11.

20. A flash drive comprising at least the slave SPI interface as recited in claim 11.

21. An master/slave serial peripheral interface (SPI) circuit comprising:

a master SPI interface including;

a master serial data output line;

a master serial data input line;

an master output interface clock line for transmitting interface clock signals;

a slave SPI interface including;

a slave serial data input line connected to the master serial data output line;

a slave serial data output line connected to the master serial data input line;

a slave input interface clock line connected to the master output interface clock line for receiving the interface clock signals from the master SPI interface;

a buffer circuit including a plurality of shift register cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to store data bits therein and to output the data bits in response to the interface clock signals;

a pointer circuit for generating a pointer for designating ones of the plurality of cells of the buffer;

wherein

the buffer circuit is operative, in response to the pointer and the interface clock signals for transmitting data bits from the designated ones of the plurality of cells to the slave serial data output line in synchronism with the interface clock signals received from the slave input interface clock line.

22. The master/slave serial peripheral interface circuit as recited in claim 21, wherein the slave SPI interface further comprises:

a bus data line of a bus of a host device comprising the slave SPI interface, and

a bus clock line of the bus configured to transmit bus clock signals;

bus control circuitry operable to load data into the buffer in response to bus clock signals.

23. The master/slave serial peripheral interface circuit as recited in claim 22, wherein the buffer comprises a plurality of FIFO cells.

24. The master/slave serial peripheral interface circuit as recited in claim 23, wherein each of the plurality of FIFO cells comprises a shift register responsive to the interface clock signals to shift data bits stored therein.

25. An electronic device comprising at least the slave SPI interface as recited in claim 21.

26. A portable audio player comprising at least the slave SPI interface as recited in claim 21.

27. A mobile telephone comprising at least the slave SPI interface as recited in claim 21.

28. A flash drive comprising at least the slave SPI interface as recited in claim 21.

29. A slave interface in a master/slave peripheral interface SPI circuit having a master SPI, the slave interface comprising:

a slave SPI interface including;

a slave serial data input line;

a slave serial data output line;

a slave input interface clock line connectable to receive interface clock signals from the master SPI interface;

a buffer having a plurality of cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to output data bits in response to the interface clock signals;

a multiplexer having inputs connectable to outputs of each of the plurality of cells of the buffer and an output provided as the slave serial data output line;

a demultiplexer having an input connectable to receive the interface clock signals and outputs connected to the clock inputs of the plurality of cells;

a read pointer processing circuit for generating a read pointer;

the multiplexer connected to receive the read pointer for connecting as an input thereto only a selected output of a cell designated by the read pointer;

the demultiplexer connected to receive the read pointer for connecting the interface clock signals from the serial input interface clock line connected to a master output interface clock line to only a selected output thereof for feeding the interface clock signals to the clock input of the cell designated by the read pointer;

the clock input of the cell designated by the read pointer receiving the interface clock signals and outputting the data bits stored therein in synchronism with the interface clock signals,

wherein

the multiplexer outputs the data bits stored in the cell designated by the read pointer over the slave serial data output line in synchronism with the interface clock signals without reference to a dedicated high frequency clock signal.

30. An electronic device incorporating the slave SPI interface as recited in claim 29.

31. A portable audio player incorporating the slave SPI interface as recited in claim 29.

32. A mobile telephone incorporating the slave SPI interface as recited in claim 29.

33. A flash drive incorporating the slave SPI interface as recited in claim 29.

34. The slave interface as recited in claim 29 further comprises:

a bus data line input for receiving the data bits from a host device, and

a bus clock line input for receiving bus clock signals of the host device;

bus control circuitry operable to load the data bits into the buffer in response to bus clock signals.

35. The slave interface as recited in claim 34, wherein the buffer comprises a plurality of FIFO cells.

36. The slave interface as recited in claim 35, wherein each of the plurality of FIFO cells comprises a shift register responsive to the interface clock signals to shift the data bits stored therein.

37. The slave interface as recited in claim 36, wherein the bus control circuitry comprises:

a first demultiplexer having an input connectable to receive the bus clock signals and outputs connectable to clock inputs of the FIFO cells of the buffer;

a second demultiplexer having an input connectable to the bus data line input for receiving the data bits to be stored and outputs connected to the inputs of the plurality of cells;

a bus circuit for generating a write pointer;

the first demultiplexer connected to receive the write pointer for connecting the bus clock signals to only a designated output thereof for feeding the bus clock signals to the cell designated by the write pointer;

the second demultiplexer connected to receive the write pointer for connecting the data bits only to a designated output thereof for feeding the data bits to the cell designated by the write pointer.

38. A slave interface in a master/slave serial peripheral interface SPI circuit having a master SPI interface, the slave interface comprising:

a slave SPI interface including;

a slave serial data input line;

a slave serial data output line;

a slave input interface clock line connectable to receive interface clock signals from the master interface;

a buffer having a plurality of cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to store data bits therein and to output the data bits in response to the interface clock signals;

means for designating ones of the plurality of cells of the buffer;

means, responsive to the interface clock signals, for transmitting the data bits from the designated one of the plurality of cells to the slave serial data output line in synchronism with the interface clock signals received from the slave input interface clock line.

39. A slave interface in a master/slave serial peripheral interface (SPI) circuit having a master interface, the slave interface comprising:

a slave SPI interface including;

a slave serial data input line;

a slave serial data output line;

a slave input interface clock line connectable to receive interface clock signals from the master interface;

a buffer circuit including a plurality of shift register cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to store data bits therein and to output the data bits in response to the interface clock signals;

a pointer circuit for generating a pointer for designating ones of the plurality of cells of the buffer;

wherein

the buffer circuit is operative, in response to the pointer and the interface clock signals for transmitting data bits from the designated ones of the plurality of cells to the slave serial data output line in synchronism with the interface clock signals received from the slave input interface clock line.

40. In a slave interface, a method of transmitting data from the slave interface to a master interface over a serial peripheral interface (SPI) comprising:

storing data bits in a plurality of shift register cells of a buffer, each shift register cell having clock inputs;

receiving interface clock signals from the master interface;

designating one of the plurality of cells of the buffer;

feeding the interface clock signals to the clock inputs of only the designated one of the plurality of cells of the buffer;

serially transmitting the data bits form only the designated one of the plurality of cells to the master interface in synchronism with the interface clock signals received from the master interface;

designating another of the plurality of cells of the buffer;

feeding the interface clock signals to the clock inputs of only the designated another of the plurality of cells of the buffer; and

serially transmitting the data bits from only the designated another of the plurality of cells to the master interface in synchronism with the interface clock signals received from the master interface.