Ultra low power sleep mode

• US 8,510,584 B1
• Filed: 11/15/2011
• Issued: 08/13/2013
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Luciano Processing LLC (Intellectual Ventures LLC)
• Inventors: Wright, David G.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US13/296,977
• Time in Patent Office: 637 Days
• Field of Search: 713/320, 713/323, 713/324, 711/109
• US Class Current: 713/323
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit in accordance with one embodiment of the invention can include a plurality of storage elements that can be coupled in a first mode and a second mode. The first mode includes the plurality of storage elements being coupled to enable normal operation of the integrated circuit, and the second mode includes the plurality of storage elements being coupled together as a shift register. The integrated circuit also includes a rewritable non-volatile memory and a sleep controller that is coupled to the rewritable non-volatile memory. The sleep controller is for switching the plurality of storage elements between the first mode and the second mode. The sleep controller is for extracting data from the plurality of storage elements in the second mode and storing the data with the non-volatile memory to record the operating state of the plurality of storage elements in the first mode.

Claims

1. An integrated circuit comprising:

a plurality of storage elements having a first configuration to store data during normal operations of the integrated circuit; and

a sleep controller configured to switch between the first configuration and a second configuration for the plurality of storage elements in response to an indication of a power mode change for the integrated circuit, wherein the sleep controller is configured to extract data from or record data to the plurality of storage elements configured as a shift register in the second configuration.

2. The integrated circuit of claim 1, further comprising:

a power controller coupled to the sleep controller, the power controller being configured to control when power is provided to at least a portion of the integrated circuit.

3. The integrated circuit of claim 2, wherein the power controller is configured to detect a wake event for the integrated circuit and configured to allow power to flow to the integrated circuit in response to a detection of the wake event.

4. The integrated circuit of claim 3, wherein the power controller is configured to notify the sleep controller of detection of the wake event.

5. The integrated circuit of claim 2, wherein the sleep controller is configured to cause the power controller to restrict power to at least the portion of the integrated circuit.

6. The integrated circuit of claim 1, wherein the plurality of storage elements in the first configuration are coupled to function as a state machine.

7. A method comprising:

detecting a trigger event during normal operation of an integrated circuit;

in response to the trigger event, reconfiguring a plurality of storage elements from a first configuration into a second configuration comprising the plurality of storage elements being coupled together as a shift register;

in response to the trigger event, extracting data from the plurality of storage elements configured as the shift register; and

restricting power to the plurality of storage elements after extracting the data from the plurality of storage elements.

8. The method of claim 7, wherein the trigger event comprises a sleep mode initiation.

9. The method of claim 7, wherein the trigger event comprises a power interruption to the integrated circuit.

10. The method of claim 7, wherein the integrated circuit comprises a microcontroller.

11. The method of claim 7, wherein the first configuration of the plurality of storage elements comprises the plurality of storage elements being coupled to enable operation of the integrated circuit.

12. The method of claim 7, further comprising storing the data.

13. The method of claim 12, wherein storing the data records an operating state of the plurality of storage elements in the first configuration.

14. The method of claim 7, wherein during the normal operation of the integrated circuit, the plurality of storage elements are coupled to function as a state machine.

15. A method comprising:

detecting a wake event for an integrated circuit;

in response to the wake event, loading data into a plurality of storage elements configured as a shift register, wherein the data corresponds to an operational state for the plurality of the storage elements; and

reconfiguring the plurality of storage elements from the shift register into a different configuration in response to the wake event and after loading the data into the plurality of the storage elements.

16. The method of claim 15, wherein the wake event comprises receiving a signal via a pin of the integrated circuit.

17. The method of claim 15, wherein the integrated circuit comprises a microcontroller.

18. The method of claim 15, wherein the plurality of storage elements comprises a scan chain.

19. The method of claim 15, further comprising resuming the operating state of the plurality of storage elements in the different configuration.

20. The method of claim 15, wherein the plurality of storage elements are coupled to function as a state machine in the different configuration.