Changing abstraction level of portion of circuit design during verification

• US 8,510,693 B2
• Filed: 05/11/2012
• Issued: 08/13/2013
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited, Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Sato, Hiroyuki, Kikuta, Hideo
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/469,944
• Publication Number:
  US 20120317526A1
• Time in Patent Office: 459 Days
• Field of Search: 716/103, 716/106, 716/111
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

A design verification method is disclosed. A computer searches for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks. Then, the computer changes an abstraction level of an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist.

Claims

1. A design verification method performed in a computer, the method comprising:

searching for, by the computer, a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks;

selecting, by the computer, first operation description data from multiple sets of operation description data describing, in different abstractions, an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist; and

changing, by the computer, an abstraction level of the operation of the out-of-path block by replacing second operation description data described in the netlist with the first operation description data.

2. The design verification method as claimed in claim 1,

wherein the operation of the out-of-path block in the netlist is changed by the first operation description data of a higher abstraction level than other operation description data by using a model database which is stored in the storage part and stores the first operation description data and the other operation description data describing the operation with abstraction levels respective to different verification accuracies related to the block.

3. The design verification method as claimed in claim 2,

wherein the model database stores the multiple sets of operation description data describing operations respective to verification purposes related to the same block;

and

the computer further changes the operation of an in-path block which is a block in the path and is described in the netlist, with a set of operation description data describing the operation respective to a verification purpose by using the model database.

4. The design verification method as claimed in claim 3, further comprising:

classifying, by the computer, the multiple blocks into the in-path block and the out-of-path block by referring to the path being searched and the netlist.

5. The design verification method as claimed in claim 4, further comprising:

creating and storing, by the computer, an in-path block list which lists one or more in-path blocks being searched, in the storage part;

creating and storing, by the computer, an out-of-path block list which lists blocks excluded from the in-path block list, by referring to the netlist; and

changing, by the computer, the abstraction level of the operation of the out-of-path block which is searched, the operation described in the netlist, by referring to the out-of-path block list stored in the storage part.

6. The design verification method as claimed in claim 1,

wherein the first operation description data and connection information of the out-of-path bock are deleted from the netlist, to change the abstraction level of the operation of the out-of-path block to be higher than the description.

7. A non-transitory computer-readable recording medium storing a program which, when executed by a computer, causes the computer to perform a design verification process, the process comprising:

searching for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks;

selecting first operation description data from multiple sets of operation description data describing, in different abstractions, an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist; and

changing an abstraction level of the operation of the out-of-path block by replacing second operation description data described in the netlist with the first operation description data.

8. A design verification apparatus, comprising:

a storage part configured to store a netlist in which a connection relationship between multiple blocks forming a circuit and an operation of each of the multiple blocks;

a searching part configured to search for a path in accordance with the connection relationship between the multiple blocks by referring to the netlist from the storage part based on terminal information concerning a verification of the circuit;

a selecting part configured to select first operation description data from multiple sets of operation description data describing, in different abstractions, an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist; and

a changing part configured to change an abstraction level of the operation of the out-of-path block by replacing second operation description data described in the netlist with the first operation description data.