Structure and method to improve threshold voltage of MOSFETs including a high k dielectric

• US 8,513,085 B2
• Filed: 03/01/2012
• Issued: 08/20/2013
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Fang, Sunfei, Greene, Brian J., Leobandung, Effendi, Liang, Qingqing, Maciejewski, Edward P., Wang, Yanfeng
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/409,693
• Publication Number:
  US 20120168874A1
• Time in Patent Office: 537 Days
• Field of Search: 438/585, 438/775, 438/776, 257/E21.194, 257/371, 257/407
• US Class Current: 438/371
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

Claims

1. A semiconductor structure comprising:

at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, a patterned threshold voltage adjusting layer and a patterned gate conductor, wherein said patterned threshold voltage adjusting layer is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material; and

a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material, said conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm.

2. The semiconductor structure of claim 1 further comprising an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of the at least one patterned gate stacks.

3. The semiconductor structure of claim 1 wherein said conformal nitride-containing liner has an upper surface that extends above an upper surface of the patterned gate conductor of said at least one patterned gate stack.

4. The semiconductor structure of claim 1 wherein said patterned gate dielectric and said patterned gate conductor have sidewalls that are vertically coincident.

5. A semiconductor structure comprising:

at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and

a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material, said conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm, wherein said conformal nitride-containing liner has an upper surface that does not extend above an upper surface of said patterned gate dielectric material.

6. The semiconductor structure of claim 5 further including a patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor, wherein said patterned threshold voltage adjusting layer includes a pFET threshold voltage adjusting material selected from Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, and TiO₂.

7. The semiconductor structure of claim 5 further including a patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor, wherein said patterned threshold voltage adjusting layer is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

8. The semiconductor structure of claim 5 further comprising an inner liner located on the upper surface of said conformal nitride-containing liner, said inner liner having one vertical edge in contact with a remaining vertical sidewall portion of said at least one patterned gate stack.

9. The semiconductor structure of claim 8 further comprising an oxide liner located on another vertical edge of said inner liner and on an uppermost surface of said inner liner, but not in contact with an outer vertical edge of said conformal nitride-containing liner.

10. The semiconductor structure of claim 9 further comprising an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of the at least one patterned gate stacks.

11. A semiconductor structure comprising:

a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, wherein said first patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, a first patterned threshold voltage adjusting layer and a patterned gate conductor and said second patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, a second patterned threshold voltage adjusting layer and a patterned gate conductor, wherein one of the first or second patterned threshold voltage adjusting layers is a pFET threshold voltage adjusting material selected from Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, and TiO₂ and the other of said first or second patterned threshold voltage adjusting layers not including a pFET threshold voltage adjusting material is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material; and

a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material in both device regions, the conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm.

12. The semiconductor structure of claim 11 further comprising an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of one of the patterned gate stacks.

13. The semiconductor structure of claim 11 wherein said conformal nitride-containing liner in both device regions has an upper surface that extends above an upper surface of each patterned gate conductor of said first and second patterned gate stacks.

14. The semiconductor structure of claim 11 wherein said patterned gate dielectric and said patterned gate dielectric in each device region have sidewalls that are vertically coincident.

15. A semiconductor structure comprising:

a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, wherein said first patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and

a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material in both device regions, the conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm, wherein said conformal nitride-containing liner in each device region has an upper surface that does not extend above an upper surface of each patterned gate dielectric material.

16. The semiconductor structure of claim 15 further comprising a first patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the first patterned gate stack and a second patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the second patterned gate stack wherein one of the first or second patterned threshold voltage adjusting layers is a pFET threshold voltage adjusting material selected from Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, and TiO₂.

17. The semiconductor structure of claim 16 wherein the other of said first or second patterned threshold voltage adjusting layers not including a pFET threshold voltage adjusting material is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

18. The semiconductor structure of claim 15 further comprising an inner liner located on the upper surface of said conformal nitride-containing liner in each device region, said inner liner having one vertical edge in contact with a remaining vertical sidewall portion of said first and second patterned gate stacks.

19. The semiconductor structure of claim 18 further comprising an oxide liner located on another vertical edge of said inner liner and on an uppermost surface of said inner liner, but not in contact with an outer vertical edge of said conformal nitride-containing liner.

20. The semiconductor structure of claim 19 further comprising an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of the said first and second patterned gate stacks.