Method of forming bump structure having tapered sidewalls for stacked dies

• US 8,513,119 B2
• Filed: 12/10/2008
• Issued: 08/20/2013
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Hsu, Kuo-Ching, Chen, Chen-Shien, Chiou, Wen-Chih, Yu, Chen-Hua
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US12/331,900
• Publication Number:
  US 20100140805A1
• Time in Patent Office: 1,714 Days
• Field of Search: 438/667, 257/E21.577, 257/E21.585
• US Class Current: 438/667
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1401 Structure
• CPC Class Codes: H01L 2224/1701 Structure
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/812 : Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a first semiconductor substrate, the first semiconductor substrate having a through via extending from a first side into the first semiconductor substrate, the through via being conductive;

exposing, after the providing, the through via on a second side of the first semiconductor substrate;

forming, after the exposing, a first isolation film along a top surface of the second side of the first semiconductor substrate such that the through via is exposed;

forming, after the forming the first isolation film, a conductive element with tapered sidewalls on the through via, the conductive element being positioned on the top surface of the second side;

forming a second isolation film on the first isolation film, the first isolation film and the second isolation film being formed of different materials, and wherein the second isolation film is formed on, and covers, at least a portion of a first side of the conductive element; and

forming a contact barrier layer after forming the second isolation film, the contact barrier layer formed over at least a portion of a second side of the conductive element and a portion of the top surface of the conductive element.

2. The method of claim 1, wherein the forming the conductive element comprises using a patterned mask with re-entrant openings as a mold for the conductive element.

3. The method of claim 2, wherein the forming the conductive element further comprises forming the patterned mask with re-entrant openings by applying a mask layer and removing portions of the mask layer to form the re-entrant openings.

4. The method of claim 1, wherein the exposing the through via comprises etching the first semiconductor substrate below a surface of the through via such that the through via protrudes from the first semiconductor substrate.

5. The method of claim 1, wherein the forming the first isolation film comprises forming a layer of insulating material, planarizing the layer of insulating material, and etching the layer of insulating material to expose the through via.

6. The method of claim 1, wherein the through via protrudes from the first isolation film.

7. The method of claim 1, wherein the forming the conductive element comprises:

forming a seed layer over the first isolation film and the through via;

forming a patterned mask over the seed layer, the patterned mask having re-entrant openings exposing the seed layer over the through via;

forming a metal pad over exposed portions of the seed layer;

removing the patterned mask; and

removing exposed portions of the seed layer.

8. The method of claim 1, further comprising removing a liner from exposed portions of the through via.

9. A method of forming a semiconductor device, the method comprising:

providing a first semiconductor substrate having a plurality of through vias extending from a circuit-side to a backside of the first semiconductor substrate, a conductive pad having tapered sidewalls being located over each of the plurality of through vias on a top surface of the backside such that the conductive pad has a larger width closest to the through vias than a region farther from the through vias, the backside of the first semiconductor substrate having a first isolation film on the top surface of the backside and a second isolation film on the first isolation film and covering a first sidewall of the conductive pad, the conductive pad having a contact barrier layer covering a second sidewall and a portion of the top surface of the conductive pad;

providing a second semiconductor substrate having a plurality of top contacts; and

bonding the first semiconductor substrate to the second semiconductor substrate such that each of the plurality of top contacts of the second semiconductor substrate are electrically coupled with respective ones of the conductive pads on the first semiconductor substrate.

10. The method of claim 9, wherein at least some of the conductive pads comprise a redistribution line, and wherein the second isolation film covers at least a portion of the conductive pads.

11. The method of claim 10, wherein the redistribution line is between the first isolation film and the second isolation film.

12. The method of claim 9, wherein the bonding is performed at least in part by a metal bump.