Edge connect wafer level stacking with leads extending along edges

• US 8,513,789 B2
• Filed: 02/09/2007
• Issued: 08/20/2013
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): HENRY, CALEB E
• Application Number:
  US11/704,713
• Publication Number:
  US 20080083976A1
• Time in Patent Office: 2,384 Days
• Field of Search: 257/678
• US Class Current: 257/678
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Claims

1. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements with a second subassembly including a plurality of microelectronic elements, the microelectronic elements of each subassembly having faces and being attached to one another at a plurality of saw lanes such that a first saw lane of the saw lanes extends in a first direction parallel to the faces of the microelectronic elements and separates adjacent first and second microelectronic elements of each subassembly in a second direction parallel to the faces of the first and second microelectronic elements and transverse to the first direction, wherein each of the first and second adjacent microelectronic elements of the first and second subassemblies has a plurality of electrically conductive traces extending towards the first saw lane;

forming notches in the first and second subassemblies of the microelectronic assembly, the notches including a first notch having a side wall extending in the first direction along the first saw lane so as to expose the plurality of the traces of each first microelectronic element and the plurality of the traces of each second microelectronic element of each of the first and second subassemblies; and

forming a lead at the side wall of the first notch, the lead being in electrical communication with at least one trace of the first and second microelectronic elements of the first and second subassemblies; and

entirely dicing through the saw lanes of the first and second subassemblies to form individual stacked packages.

2. The method of claim 1, wherein during the step of forming the microelectronic assembly the saw lanes of the first subassembly are aligned with the saw lanes of the second subassembly and the notches are formed along the saw lanes of the respective assemblies.

3. The method of claim 1, wherein at least some of the plurality of microelectronic elements of the first and second subassemblies include contacts exposed at their respective faces, wherein at least some of the traces are electrically connected to at least some of the contacts.

4. The method of claim 1, wherein during the step of forming a microelectronic assembly a first face of the first subassembly is adhered to a second face of the second subassembly by an adhesive.

5. The method of claim 1, wherein at least some of the traces of the first subassembly are offset in the first direction from respective traces of at least some of the traces of the second subassembly in said microelectronic assembly, wherein said step of forming leads forms at least one lead in contact with no more than one of the pluralities of traces of the first and second microelectronic assemblies.

6. The method of claim 4, wherein the second subassembly includes a first face remote from the second face, wherein the contacts and the traces of the first and second subassemblies are disposed at the first faces thereof.

8. The method of claim 1, wherein the traces of the first and second microelectronic elements of the first subassembly extend to respective edges of the microelectronic elements.

9. The method of claim 1, wherein after the dicing step, at least one of the leads is electrically connected to traces extending from the microelectronic elements of the first and second subassemblies.

10. The method of claim 1, wherein during the forming step, the lead is formed such that it is in contact and in electrical communication with at least one trace of the first and second microelectronic elements of each of the first and second subassemblies.

7. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements with a second subassembly including a plurality of microelectronic elements, the microelectronic elements of each subassembly having faces and being attached to one another at a plurality of saw lanes such that a first saw lane of the saw lanes extends in a first direction parallel to the faces of the microelectronic elements and separates adjacent first and second microelectronic elements of each subassembly in a second direction parallel to the faces of the first and second microelectronic elements and transverse to the first direction, wherein each of the first and second adjacent microelectronic elements of the first and second subassemblies has a plurality of contacts and a plurality of electrically conductive traces extending towards the first saw lane;

forming notches in the first and second subassemblies of the microelectronic assembly, the notches including a first notch having a side wall extending in the first direction along the first saw lane so as to expose the plurality of the traces of each first microelectronic element and the plurality of the traces of each second microelectronic element of each of the first and second subassemblies; and

forming a lead at the side wall of the first notch, the lead being in contact and in electrical communication with at least one traces of the first and second microelectronic elements of each of the first and second subassemblies; and

entirely dicing through the saw lanes of the first and second subassemblies to form individual stacked packages.