Package-on-package interconnect stiffener

• US 8,513,792 B2
• Filed: 04/10/2009
• Issued: 08/20/2013
• Est. Priority Date: 04/10/2009
• Status: Active Grant

• Current Assignee: Intel Corporation, Intel Limited (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Ganesan, Sanka, Kanaoka, Yosuke, Viswanath, Ram S., Swaminathan, Rajasekaran, Nickerson, Robert M., Arana, Leonel R., Guzek, John S., Tomita, Yoshihiro
• Primary Examiner(s): Arroyo, Teresa M
• Application Number:
  US12/384,984
• Publication Number:
  US 20100258927A1
• Time in Patent Office: 1,593 Days
• Field of Search: 257/686, 257/723, 257/777, 257/E25.006, 257/E25.013, 257/E25.018, 257/E25.021, 257/E25.027, 257/E23.085, 257/E21.614, 257/737, 257/738, 257/773
• US Class Current: 257/686
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/488 consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

Claims

1. A semiconductor assembly, comprising:

a first semiconductor package having a plurality of inter-package contact pads on a top side and a plurality of second level interconnect (SLI) pads on a bottom side; and

a planar stiffener having a first plurality of planar contact pads on a top side of the stiffener electrically connected to a second semiconductor package, and a second plurality of planar contact pads on a bottom side of the stiffener electrically connected to the inter-package contact pads of the first semiconductor package by a solder having a melt temperature wherein said stiffener has an adhesive on the bottom side of the stiffener which attaches said stiffener to the top side of the first semiconductor package, said adhesive having a glass transition temperature between 90°

C.-180°

C. and a cure temperature below said melt temperature;

wherein said planar stiffener has a substrate comprising a polymeric core and an insulative plug material.

2. The assembly of claim 1, wherein the stiffener comprises:

said substrate having a through recess adapted to house a die electrically attached to the first package, and a plurality of through openings through which the first and second pluralities of contact pads are disposed;

a solder-wettable planar surface finish on the first and second pluralities of contact pads; and

a conductive trace electrically interconnecting the first plurality of contact pads to the corresponding second plurality of contact pads.

3. The assembly of claim 1, wherein the stiffener includes routing features located on said top side of said stiffener and connected to said first plurality of contact pads.

4. The assembly of claim 1, wherein the second plurality of contact pads of the stiffener is connected to the first package by way of conductive micro balls comprising said solder.

5. The assembly of claim 2, wherein the substrate includes a coefficient of thermal expansion (CTE) between 15 and 25 ppm, and a flexural modulus between 15 and 30 GPa.

6. The assembly of claim 1, wherein a layout of the second plurality of planar contact pads of the stiffener matches a layout of the inter-package contact pads of the first package.

7. The assembly of claim 1, wherein said plug material disposed between the first plurality and the second plurality of contact pads.

8. The assembly of claim 2, wherein said plug material disposed in the substrate of the stiffener.

9. The semiconductor assembly of claim 1 wherein said insulative plug material comprises an epoxy.

10. The semiconductor assembly of claim 1 wherein said insulative plug material comprises a silica filled epoxy composite.

11. The semiconductor assembly of claim 1 wherein said insulative plug material comprises a solder resist material.

12. The semiconductor assembly of claim 9 wherein said insulative plug material is disposed between the first plurality of planar contact pads and the second plurality of planar contact pads.

13. The semiconductor assembly of claim 9 wherein said insulative plug material is disposed between a solder resist layer formed on the top side of the stiffener and a solder resist layer formed on the bottom side of the stiffener.

14. The semiconductor assembly of claim 1 wherein said second plurality of planar contact pads on the bottom side of the stiffener are electrically connected to the inter-package contact pads of the first semiconductor package with a solder.

15. A semiconductor assembly comprising:

a first semiconductor package having a plurality of inter-package contact pads on a top side and a plurality of second level interconnect (SLI) pads on a bottom side; and

a planar stiffener having a plurality of contact pads on a top side of the stiffener electrically connected to a second semiconductor package, and a second plurality of contact pads on a bottom side of the stiffener electrically connected to the inter-package contact pads on the first semiconductor package by a solder having a melt temperature and an adhesive on the bottom side of the stiffener which attaches the stiffener to the top side of the first semiconductor package, said adhesive having a glass transition temperature between 90°

C.-180°

C. and a cure temperature below said melt temperature.

16. The assembly of claim 15 wherein the second plurality of contact pads on the stiffener is connected to the first package by a plurality of conductive microballs comprising said solder.

17. The assembly of claim 15 wherein the stiffener includes a substrate having a coefficient of thermal expansion (CTE) between 15 and 25 ppm, and a flexural modulus between 15 and 30 CPa.

18. The semiconductor assembly of claim 15 wherein the stiffener includes a solder resist layer and wherein the adhesive is attached to the solder resist layer.